CS201 Lab: Design Sequential Adder, Subtractor, and Shift Regiser

Objective of this lab:

	To investigate arithmetic circuitry. 
	Arithmetic circuits play a central role in the operation of a microprocessor.

Preparation

	Read lab lecture notes.

Lab Assignments

1. Build a 4-bit right shift register device using four D-flip-flops and some one-bit tri-state buffers.
   Make sure that you have a LD control over it.
   When LD = 0, your register will be able to do parallel loading.
   When LD = 1, it will be able to shift right one bit (i.e. SI -> Q3 -> Q2 -> Q1 -> Q0).

   Hand-In

   • The circuit of the 4-bit right shift register in the lab notes.
   • The underlying circuit of the 4-bit right shift register device. (Circuit with labeled ports)
   • The testing circuit of the 4-bit right shift register device (the box with binary switches and binary probes connected to it, also with MSB and LSB labelled.)

2. Obtain the state table, state diagram, and functions of the following sequential design.
   Implement the design and verify the state table.
   Use the 4-bit Shift Register you made to store and display the result of

   	0011 
         + 0001 
         ------
           0100  

   
   Hand-In

   • State table
   • State diagram
   • Functions
   • Results of 0011 + 0001 (stored in the 4-bit Shift Register you made with MSB and LSB labelled)

3. Obtain the state table, state diagram, and functions of the following sequential design.
   Implement the design and verify the state table.
   Use the 4-bit Shift Register you made to store and display the result of

   	0101 
         - 0011  
         ------
           0010  

   
   Hand-In

   • State table
   • State diagram
   • Functions
   • Results of 0101 - 0011 (stored in the 4-bit Shift Register you made with MSB and LSB labelled)

4. Implement the following bit sequential Adder-Subtractor design.

   
   X and Y are two operand inputs and Z is for the control signal i.e. Z is the selection bit.
   When Z has value 0, the circuit is an adder, meanwhile, the D flip-flop should be initialized to 0 for each addition.
   When Z has value 1, it performs subtraction, meawhile, the the D flip-flop should be initialized to 1 for each subtraction.

   
           Test your Adder-Subtractor circuit on the following operations and 
      	use the 4-bit Shift Register you made to store and display their results.  
   
   	(Note:	Start from the least significant bit and 
   	remember to initialize the D flip-flop accordingly)
   
   	0001 + 0011 = ? 
   
   	0101 + 0010 = ? 
   
   	0101 - 0011 = ? 
   
   	0011 - 0101 = ? 
   
   

   
   Hand-In
   • Four test cases above (results stored in the 4-bit Shift Register you made with MSB and LSB labelled)
   • Description of the testing procedure used for Question 4