A Half-adder is a combinational circuit that performs the addition of 2 bits.
Inputs: 2 input bits to be added (X, Y)
Outputs: sum bit (S)
carry bit (C)
For example:
1 + 1 = 1 0 C = 1; S = 0
1 + 0 = 0 1 C = 0; S = 1
A Full-adder is a combinational circuit that forms the arithmetic sum of 3 input bits.
Inputs: 2 input bits to be added (X, Y)
1 carry bit from previous lower significant position (Ci)
Outputs: sum bit (S)
carry bit (Ci+1)
For example:
1 + 1 + 1 = 1 1 Ci+1 = 1; S = 1
1 + 0 + 1 = 1 0 Ci+1 = 1; S = 0
Note: it takes 2 half-adders to make a full adder.
Truth Table
X Y Ci Ci+1 S
------------------------------------------
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
-------------------------------------------
Expressions
S = X XOR Y XOR Ci
Ci+1 = XY + Ci(X XOR Y)
State Table
Inputs PresentState NextState Output
X Y Ci Ci+1 S
------------------------------------------
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
-------------------------------------------
The sequetial design
A binary adder is the circuit that generates the arithmetic sum of two binary numbers of any length. The subtraction of binary numbers can be done most conveniently by means of complements of numbers. Subtraction A - B can be done by taking the 2's complement of B and adding it to A. The 2's complement can be obtained by taking the 1's complement and adding 1 to the least significant pair of bits. The 1's complement can be implemented with inverters and a 1 can be added to the sum through the input carry. The addition and subtraction operations can be combined into one common circuit by including an exclusive-OR (XOR) gate with a full-adder. A bit sequential adder-subtractor is shown in the following figure:
Input X is used to represent the bit of the binary number A. Input Y is used to represent the bit of the binary number B. The control signal Z controls the type of operation. When Z = 0 the circuit is an adder, meanwhile, the D flip-flop should be initialized to 0. When Z = 1 the circuit becomes a subtractor. The D flip-flop should be initialized to 1. The XOR gate receives input of signal bit Z and the input of the operand bit Y. When Z = 0, we have Y XOR Z = Y. ------------------------------------------------- The full adder receives the value of Y, the input carry is 0 because D flip-flop was initialized to 0, and the circuit performs A plus B. When Z = 1, we have Y XOR Z = Y' and the initial carry to 1. -------------------------------------------------------------------------------- The Y input is complemented and a 1 is added through the initial input carry. The circuit performs the operation: A plus the 2's complement of B. For unsigned numbers A and B, this gives the A - B if A >= B or 2's complement of (B - A) if A < B. For signed numbers, the result is A - B provided there is no overflow.
Build the following circuit and get yourself familiar with the loading and shifting mode.
It demonstrates the following:
1. How to use a 4 bit shift register.
2. How to use the Load and Shift modes.
3. How to show the values on each output bit to make
it easier to see what's happening in shift mode.
4. Shifting direction is SI->Q3->Q2->Q1->Q0 = SO.
With LD set to 0:
The register is in shift Right mode;
The SI (shift in bit) line is used to set the value to be
shifted into the register. Clocking is positive edge triggered.
With LD set to 1:
The register is in parallel load mode.
Inputs D0 to D3 become outputs Q0 to Q3 on the next
rising clock pulse.
It can be used to store and diplay the output of your
sequential adder, subtractor, and adder-subtractor circuits
in the lab assignment.
The D flip-flop(shown below) lets the input at D propogate through to Q on the positive going edge of the clock. The present state-next state chart illustrates the behavior of the D flip-flop. Basically Q(t+1) = D, which is the characteristic equation.
Characteristic Table Excitation Table ==================== =================== D Q(t+1) Operation Q(t) Q(t+1) D ==================== =================== 0 0 Reset 0 0 0 -------------------- ------------------- 1 1 Set 0 1 1 ==================== ------------------- 1 0 0 ------------------- 1 1 1 ===================
Copyright: Department of Computer Science, University of Regina.