Objectives of this lab:

	To investigate flip-flop characteristics. 
	To verify sequential design procedures by building a simple counter.

Preparation

	Read lab lecture notes which contains the Sequential Design Procedure.

Lab Assignments

1. Implement the following circuit to test the characteristics of a D flip flop.
   • Note:
     • Using a clock input to operate the flip-flop is rather quickly.
     • You may wish to select the slow motion of the clock OR
       to use a simple binary switch instead of a clock input device.
     • Verify the flip flop state table.
     • Q(t+1) = D, is the characteristic equation.

       

   • Questions:
     • Is a D flip-flop positive or negative edge triggered?________
     • What happens when the Set switch is set to zero?__________
     • What happens when the Reset switch is set to zero?_________
     • Does it matter what the D input is when either Set or Reset is zero?_________

2. Experimentally verify the JK flip-flop state table with the following circuit.
   Is the JK flip-flop positive or negative edge triggered?________
   Verify the Characteristic table.

                          

   Reference The characteristic equation is Q(t+1) = JQ'(t) + K'Q(t).

   
   	Characteristic Table                    Excitation Table
   	==========================            ===================
   	J  K  Q(t+1)  Operation               Q(t)  Q(t+1)  J  K
   	==========================            ===================
   	0  0  Q(t)    No Change               0     0       0  x
   	--------------------------            -------------------
   	0  1  0       Reset                   0     1       1  x
   	--------------------------            -------------------
   	1  0  1       Set                     1     0       x  1
   	--------------------------            -------------------
   	1  1  Q'(t)   Complement              1     1       x  0
   	==========================            ===================
   
   

3. Design a 3 bit counter which follows the sequence 0 -> 2 -> 3 -> 4 -> 7 -> 0.
   Note: The following are required for the lab Assignment:
   • Follow the sequential design procedure which is presented in the lab lecture notes.
   • To make marking easier, route all the unused states to state 7.
   • Use JK flip-flops in your counter circuits.
     Hand in:
     • Show your design steps and the resulting circuits in LogicWorks 5.
     • Describe your testing procedures.