Objectives of this lab:

	To investigate flip-flop characteristics. 
	To verify sequential design procedures by building a simple counter.

Preparation

	Read lab lecture notes which contains the Sequential Design Procedure.

Lab Assignments

Part One:

Background

These flip-flops are associated with memory. There are two things that you can do with memory:

1. Initialize to 1 or 0
2. Set the memory to some input value

The questions that follow are organized according to these two functions

Questions on Initialization

To initialize the "memory" you use S and R. Notice that S and R are both 1. By switching only one of them to 0, you can control the output.

1. Which switch (when set to zero) will produce a 0? (R or S)
2. Which switch (when set to zero) will produce a 1? (R or S)

Questions on Input Values

S and R should both be 1 to accept input. The input into the D-Flip Flop (D) comes out of the Q when you toggle the clock(C). In other words, the clock controls when the input gets stored (or becomes output).

1. For the D-flip flop, does the output change when the clock goes from 0 to 1 or 1 to zero? Is this a positive or negative edge?
2. For the J-K flip flop, does the output change when the clock goes from 0 to 1 or 1 to zero? Is this a positive or negative edge?
3. For the J-K flip flop, what inputs on J and K will cause the value of Q to change from 0 to 1?
4. For the J-K flip flop, what inputs on J and K will cause the value of Q to change from 1 to 0?

	Characteristic Table                    Excitation Table
	==========================            ===================
	J  K  Q(t+1)  Operation               Q(t)  Q(t+1)  J  K
	==========================            ===================
	0  0  Q(t)    No Change               0     0       0  x
	--------------------------            -------------------
	0  1  0       Reset                   0     1       1  x
	--------------------------            -------------------
	1  0  1       Set                     1     0       x  1
	--------------------------            -------------------
	1  1  Q'(t)   Complement              1     1       x  0
	==========================            ===================

Part Two:

Note: The following are required for the lab Assignment:
• Follow the sequential design procedure which is presented in the lab lecture notes.
• To make marking easier, route all the unused states to state 7.
• Use JK flip-flops in your counter circuits.
• Show your design steps and the resulting circuits.
• Describe testing procedures.