To explore STM32 value line Discovery Board peripheral devices.
Read lab lecture notes.
; GPIO Test program - Dave Duguid, 2011 ; Adapted by Guili Liu in November 2014 ;;; Directives PRESERVE8 THUMB ;;; Equates INITIAL_MSP EQU 0x20001000 ; Initial Main Stack Pointer Value ;The offboard DIP Switch will be on port A bits 0 thru 3 ;PORT A GPIO - Base Addr: 0x40010800 GPIOA_CRL EQU 0x40010800 ; (0x00) Port Configuration Register for Px7 -> Px0 ;GPIOA_CRH EQU 0x40010804 ; (0x04) Port Configuration Register for Px15 -> Px8 GPIOA_IDR EQU 0x40010808 ; (0x08) Port Input Data Register ;GPIOA_ODR EQU 0x4001080C ; (0x0C) Port Output Data Register GPIOA_BSRR EQU 0x40010810 ; (0x10) Port Bit Set/Reset Register GPIOA_BRR EQU 0x40010814 ; (0x14) Port Bit Reset Register GPIOA_LCKR EQU 0x40010818 ; (0x18) Port Configuration Lock Register ;The onboard LEDS are on port C bits 8 and 9 ;PORT C GPIO - Base Addr: 0x40011000 ;GPIOC_CRL EQU 0x40011000 ; (0x00) Port Configuration Register for Px7 -> Px0 GPIOC_CRH EQU 0x40011004 ; (0x04) Port Configuration Register for Px15 -> Px8 ;GPIOC_IDR EQU 0x40011008 ; (0x08) Port Input Data Register GPIOC_ODR EQU 0x4001100C ; (0x0C) Port Output Data Register GPIOC_BSRR EQU 0x40011010 ; (0x10) Port Bit Set/Reset Register ;GPIOC_BRR EQU 0x40011014 ; (0x14) Port Bit Reset Register ;GPIOC_LCKR EQU 0x40011018 ; (0x18) Port Configuration Lock Register ;Registers for configuring and enabling the clocks ;RCC Registers - Base Addr: 0x40021000 ;RCC_CR EQU 0x40021000 ; Clock Control Register ;RCC_CFGR EQU 0x40021004 ; Clock Configuration Register ;RCC_CIR EQU 0x40021008 ; Clock Interrupt Register ;RCC_APB2RSTR EQU 0x4002100C ; APB2 Peripheral Reset Register ;RCC_APB1RSTR EQU 0x40021010 ; APB1 Peripheral Reset Register ;RCC_AHBENR EQU 0x40021014 ; AHB Peripheral Clock Enable Register RCC_APB2ENR EQU 0x40021018 ; APB2 Peripheral Clock Enable Register ;RCC_APB1ENR EQU 0x4002101C ; APB1 Peripheral Clock Enable Register ;RCC_BDCR EQU 0x40021020 ; Backup Domain Control Register ;RCC_CSR EQU 0x40021024 ; Control/Status Register ;RCC_CFGR2 EQU 0x4002102C ; Clock Configuration Register 2 ; Times for delay routines DELAYTIME EQU 1600000 ; (200 ms/24MHz PLL) ;DELAYTIME EQU 160000 ; (20 ms/24MHz PLL) ;DELAYTIME EQU 16000 ; (2 ms/24MHz PLL) ;DELAYTIME EQU 800000 ; (100 ms/24MHz PLL) ;DELAYTIME EQU 80000 ; (10 ms/24MHz PLL) ;DELAYTIME EQU 8000 ; (1 ms/24MHz PLL) ; Vector Table Mapped to Address 0 at Reset AREA RESET, Data, READONLY EXPORT __Vectors __Vectors DCD INITIAL_MSP ; stack pointer value when stack is empty DCD Reset_Handler ; reset vector AREA MYCODE, CODE, READONLY EXPORT Reset_Handler ENTRY Reset_Handler ;; Enable peripheral clocks for various ports and subsystems ; Bit 4: Port C, Bit 3: Port B, Bit 2: Port A gpio_clk_ena ldr R6, = RCC_APB2ENR ; R6 is pointer to register mov R0, #0x001C ; To turn on clocks for Ports A through C str R0, [R6] ; Turn on clocks for Ports A through C gpio_init ;; Set the config and mode bits for Port A bits 0 through 3 to ;; Floating Input ldr R6, = GPIOA_CRL ldr R0, = 0x44444444 ; CNF: 01, Mode: 00 str R0, [R6] ;; Set the config and mode bits for Port C bit 9/8 so they will ;; be push-pull outputs (up to 50 MHz) ldr R6, = GPIOC_CRH ldr R0, = 0x44444433 ; CNF: 00, Mode: 11 str R0, [R6] ;; Load R2 and R3 with the "on" and "off" constants ;mov R2, #0x0100 ; To turn PC8 on (STM DISCOVERY) ;mov R3, #0x0200 ; To turn PC9 on (STM DISCOVERY) ALIGN main mov R0, #0x0000 Wait_For_Input LDR R8, = GPIOA_IDR ;Port A Input Data Register 1. Read the input from Port A 2. Check if the bit 0 is 1, if yes, branch to BlueGreenBlink otherwise branch to Wait_For_Input BlueGreenBlink 1. Set PC8 only, turn on BLUE LED 2. Delay 3. Set PC9 only, turn on GREEN LED 4. Delay 5. Turn both LEDs off b main ALIGN delay PROC 6. Complete the delay procedure ALIGN ENDP ALIGN END
Friday, 21-Aug-2020 15:22:38 CST |
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