# Design adders & other devices

## Objectives

```  <1> implement a half-adder as a device
<2> use this half-adder to create other circuits such as:

<3> implement a full adder as a device
<4> use the full adder device to implement a 4-bit parallel adder
<5> implement a 4-bit right shift register device
<6> design a 4-bit multiplier circuit
```

## Lab Assignments

1. Following the notes in the lab, you should have completed the half adder device.
Use the device (the box) and connect binary probes and switches to ensure that the truth table is correct.
Write the boolean functions for sum and carry beside the circuit

Hand-In

• The underlying circuit of the "Half Adder" device. (Circuit with labeled ports--Part 1 in the notes)
• Boolean functions for Sum and Carry
• The "Half Adder" device (the box) with binary switches and binary probes connected to it

2. As mentioned in the notes, a full adder can be designed using two "Half Adder" devices and one additional gate.
(Hint ci+1= the sum of the carries out of the two half adders).
Build and test your circuit with the truth table.
Write the boolean functions for sum and the carry beside the circuit.
Build a full adder device and test it. You will need it to build a 4-bit parallel adder.

Hand-In

• Boolean functions for Sum and Carry for the full adder
• The underlying circuit of the "Full Adder" device. (Circuit with labeled ports--Part 1 in the notes)
• The "Full Adder" device (the box) with binary switches and binary probes connected to it

3. Build a 4-bit parallel adder device by using four "Full Adder" devices.
For this, you will use the "Full Adder" device that you just built in the last step.
```
0101 + 0010 = ?
0110 + 0011 = ?
and any other examples of your choice
```

Hand-In

• The underlying circuit of the "4-bit Parallel Adder" device. (Circuit with labeled ports)
• The 4-bit Parallel Adder device testing circuit with the above examples.
• Inputs are provided with the binary switches and the outputs will be displayed with the binary probes.
The Hex Keyboard and Hex Display can be used too.

4. Build a 4-bit right shift register device using four D-flip-flops and some one-bit tri-state buffers.
Make sure that you have a LD control over it.
When LD = 1, it will be able to shift right one bit (i.e. SI -> Q3 -> Q2 -> Q1 -> Q0).

Here is some info about the one-bit tri-state buffer for your reference:
1).A one-bit tri-state buffer can be obtained from the "Simulation Logic.clf" libruary.
2).A testing circuit and its truth table are as follows:

Hand-In

• The underlying circuit of the 4-bit right shift register device. (Circuit with labeled ports)
• The testing circuit of the 4-bit right shift register device, the box with binary switches and binary probes connected to it

5. Design a 4-bit multiplier using your 4-bit parallel adder device and the 4-bit right shift register device above with an additional D-flip-flop.
• The diagram below shows an unsigned integer multiplier.
• Build the circuit in Logicworks using:
• 4 bit data paths
• hex keyboards for setting the initial values of the Multiplicand and Multiplier register Q
• switches for controlling the shifting and the loading of the A register
• switches for controlling the shifting and loading of the Q register
• switches to control the loading and clearing of the C register (the C register can be a D flip-flop)
• hex displays and binary probe to show the results
• show the contents of B*D (i.e. 1011*1101 ) at each stage of the multiplication

• Hardware Approach for your reference
• ```
Algorithm  of (M x Q):

1.      Initilization:
A (n-bit) = 0;
C (1-bit) = 0;
Counter   = n;

2.      Repeat the following steps until Counter = 0:
a) If Q0 (LSB of Q) = 1, then C A = A + M, and
Shift C, A, and Q one bit to the right simultaneously.
b) If Q0 (LSB of Q) = 0, then
shift C, A, and Q one bit to the right simultaneously.
c) Counter = Counter - 1.

3.      Halt.  The product is in A and Q.

```
• Hand in the following:
• Make a table to show the result and operation at each stage of the multiplication.
• Print out your circuits at the initial stage, the final stage and any two stages in between.

Copyright: Department of Computer Science, University of Regina.