
Following the notes in the lab, you should have completed the half adder device.
Use the device (the box) and connect binary probes and switches to ensure that the truth table is correct.
Write the boolean functions for sum and carry beside the circuit
HandIn
 The underlining circuit of the "Half Adder" device. (Circuit with labeled portsPart 1 in the notes)
 Boolean functions for Sum and Carry
 The "Half Adder" device (the box) with binary switches and binary probes connected to it
 As mentioned in the notes, a full adder can be designed using two "Half Adder" devices and one additional gate.
(Hint c_{i+1}= the sum of the carries out of the two half adders).
Build and test your circuit with the truth table.
Write the boolean functions for sum and the carry beside the circuit.
Build a full adder device and test it. You will need it to build a 4bit parallel adder.
HandIn
 Full adder circuit using two "Half Adder" devices and one additional gate
 Boolean functions for Sum and Carry for the full adder
 The underlining circuit of the "Full Adder" device. (Circuit with labeled portsPart 1 in the notes)
 The "Full Adder" device (the box) with binary switches and binary probes connected to it
 Build a 4bit parallel adder device by using four "Full Adder" devices.
For this, you will use the "Full Adder" device that you just built
in the last step.
Test your 4bit parallel adder device with the following examples:
0101 + 0010 = ?
0110 + 0011 = ?
and any other examples of your choice
HandIn
 The underlining circuit of the "4bit Parallel Adder" device. (Circuit with labeled ports)
 The 4bit Parallel Adder device testing circuit with the above examples.
 Inputs are provided with the binary switches
and the outputs will be displayed with the binary probes.
The Hex Keyboard and Hex Display can be used too.
 Build a 4bit right shift register device using four Dflipflops
and some onebit tristate buffers.
Make sure that you have a LD control over it.
When LD = 0, your register will be able to do parallel loading.
When LD = 1, it will be able to shift right one bit (i.e. SI > Q3 > Q2 > Q1 > Q0).
Here is some info about the onebit tristate buffer for your reference:
1).A onebit tristate buffer can be obtained from the "Simulation Logic.clf" libruary.
2).A testing circuit and its truth table are as follows:
HandIn
 The underlining circuit of the 4bit right shift register device. (Circuit with labeled ports)
 The testing circuit of the 4bit right shift register device, the box with binary switches and binary probes connected to it
 Design a 4bit multiplier using your 4bit parallel adder device and the 4bit right shift register device above with an additional Dflipflop.
 The diagram below shows an unsigned integer multiplier.
 Build the circuit in Logicworks using:
 4 bit data paths
 hex keyboards for setting the initial values of the Multiplicand and Multiplier register Q
 switches for controlling the shifting and the loading of the A register
 switches for controlling the shifting and loading of the Q register
 switches to control the loading and clearing of the C register (the C register can be a D flipflop)
 hex displays and binary probe to show the results
 show the contents of B*D (i.e. 1011*1101 ) at each stage of the multiplication
 Hardware Approach for your reference
Algorithm of (M x Q):
1. Initilization:
A (nbit) = 0;
C (1bit) = 0;
Counter = n;
2. Repeat the following steps until Counter = 0:
a) If Q0 (LSB of Q) = 1, then C A = A + M, and
Shift C, A, and Q one bit to the right simultaneously.
b) If Q0 (LSB of Q) = 0, then
shift C, A, and Q one bit to the right simultaneously.
c) Counter = Counter  1.
3. Halt. The product is in A and Q.
 Hand in the following:
 Make a table to show the result and operation at each stage of the multiplication.
 Print out your circuits at the initial stage, the final stage and any two stages in between.