Introduction to VHDL in LogicWorks 5
- Learn VHDL Basic Structure
- Create VHDL Model for a Device Symbol
"LogicWorks is an interactive circuit design tool intended for teaching
and learning digital logic." LogicWorks 5 is the newest version of LogicWorks.
It is a program that we can use for designing and simulating circuits.
VHDL stands for VHSIC Hardware Description Language.
VHSIC means Very High Speed Integrated Circuits.
VHDL is an industry-standard language for modeling and synthesizing digital
hardware, particularly for programmerable logic or Application Specific
Integrated Circuits. The VHDL simulation serves as a basis for testing
complex designs and validating the design prior to fabrication. As a result,
the redesign is reduced, the design cycle is shortened, and the product is
brought to market sooner.
A VHDL program can be considered as a description of a digital system;
the associated simulator will use this description to produce behavior
that will mimic that of the physical system.
This lab contains the basic structure of VHDL
and creating a VHDL model for a device symbol.
1. VHDL Basic Structure
VHDL can be used to describe digital hardware at different levels
of abstraction. It can be used as a tool to enter Boolean equations
and truth tables. Some other techniques will be introduced in the
Entity and Architecture
An entity declaration and an architecture body are the two
very basic constructs that are required by every VHDL file.
The entity declaration defines the inputs and outputs of the design.
The architecture body defines the relationship between the inputs and
For this simple circuit
we can use the following VHDL to describe it.
Pay attention to the use of entity declaration and
architecture body constructs.
We have learnt that a 3-input majority detector has the following
a b c y
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
The corresponding Boolean function of it is
y = ab + bc + ac
The following is the VHDL code to describe this 3-input majority detector.
The Boolean operators, AND, OR, NAND, XOR and XNOR
are simply represented by those words. VHDL has an equal
order of precedence for these Boolean operators,
so everything must be written explicitly with parentheses.
2. Create a VHDL Model for a Device Symbol
We will now look at how we can use VHDL to describe the operation
of a device that is going to be in a LogicWorks circuit diagram.
- Open LogicWorks 5.
- Close any open circuit diagrams or VHDL files if any.
- Go to the File menu and select the New command.
- In the list of available document types,
select Model Wizard and click OK.
- For the Source selection, choose "Create a new,
- For the Destination selection, choose
"Create a new symbol with the specified model attached."
- Click the Next button.
- Select the VHDL model type, and enter a name, such as,
- Click on the Next button to view the
"Port Interface Panel".
- Set the Functions to Input. if it isn't already.
- Enter the name a as the first input.
The note above about names in VHDL applies also to input and output
names, so you have to be sure to use something that is not a reserved
- Click Add Single Bit button.
- Enter the name b, and click the Add Single Bit
button again to add the second inpuit.
- Enter the name c, and click the Add Single Bit
button again to add the third inpuit.
- Go back to the top of the panel and change the Function
selection to Output.
- Enter the name y, and click the Add Single Bit
- The port list should now look like this:
- Click on the Next button, you should see this panel.
It allows you to specify where the pins will appear on the
schematic symbol. By default, inputs are on the left and the outputs
on the right, which should make sense for most applications.
- If desired, move the pins to different locations on the
symbol by dragging and dropping names from one box
- Once you are satisfied with the pin locations,
click on the Next button, you should see this panel.
- Click on New Lib button to create a new one on your
I: drive, for example I:\301\mylib.
If you want to open a existing work library,
Click on Open Lib button to open one.
- Once you have selected a library, click on the Finish
A standard Save As box will appear asking you to
save the VHDL model file. This step is necessary because the
name of the file will be stored with the component.
- Save majority3.dwv model file in the
default location, or find a suitable folder for it.
The Model Wizard has now created a VHDL model file that describes
all the inputs and outputs, but has no actual behavior. It has also
created a device symbol with entries linking to it to the file.
We now have two steps left: first to fill in the actual behavior part
of the VHDL model, and then to build a test circuit to make it work.
- Select the New command in the File menu;
then choose the Circuit item.
This will creat a new, empty
circuit window on the screen.
- Locate the majority3 part in the parts list on the
right hand side of the screen,
and place it in the circuit
window, you should see this part:
- Double-click on the majority3 device. This will open the
the VHDL model in a new window.
- Refer to Example 2 to get the architecture
- Compile the VHDL Model.
- Close the majority3 document window,
once the file is compiled correctly.
- You should now be looking at the circuit containing majority3
The system description is now complete,
so we just have to test it.
- Connect a binary switch to a, b, c and a binary probe
- Change the values for a, b, c and record the values of the
Check if it matches the truth table for the
3-input majority testector.
- You should have this circuit.
By now, you have learned the basic ideas about VHDL with LogicWorks,
but there is much more to learn. This lab material is only an introduction
to VHDL with LogicWorks 5. More about VHDL will be introduced in the
future labs. There are some LogicWorks 5 manuals available.
If you want to work through more tutorials in the manual or
want to know more, you can ask me during the lab.
You may also ask me questions at lab time or at my office hours
in CL119. If a lab requires new features, I will explain more
within the lab.
LogicWorks is a trademark of Capilano Computing.
Copyright: Department of Computer Science, University of Regina.