"LogicWorks is an interactive circuit design tool intended for teaching and learning digital logic." LogicWorks 5 is the newest version of LogicWorks. It is a program that we can use for designing and simulating circuits.
VHDL stands for VHSIC Hardware Description Language. VHSIC means Very High Speed Integrated Circuits. VHDL is an industry-standard language for modeling and synthesizing digital hardware, particularly for programmerable logic or Application Specific Integrated Circuits. The VHDL simulation serves as a basis for testing complex designs and validating the design prior to fabrication. As a result, the redesign is reduced, the design cycle is shortened, and the product is brought to market sooner. A VHDL program can be considered as a description of a digital system; the associated simulator will use this description to produce behavior that will mimic that of the physical system.
This lab contains the basic structure of VHDL and creating a VHDL model for a device symbol.
we can use the following VHDL to describe it.
Pay attention to the use of entity declaration and architecture body constructs.
a b c y --------- 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 1 --------The corresponding Boolean function of it is
y = ab + bc + acThe following is the VHDL code to describe this 3-input majority detector.
NOTE: The Boolean operators, AND, OR, NAND, XOR and XNOR are simply represented by those words. VHDL has an equal order of precedence for these Boolean operators, so everything must be written explicitly with parentheses.
We will now look at how we can use VHDL to describe the operation of a device that is going to be in a LogicWorks circuit diagram.
The note above about names in VHDL applies also to input and output names, so you have to be sure to use something that is not a reserved word.
It allows you to specify where the pins will appear on the schematic symbol. By default, inputs are on the left and the outputs on the right, which should make sense for most applications.
If you want to open a existing work library, Click on Open Lib button to open one.
A standard Save As box will appear asking you to save the VHDL model file. This step is necessary because the name of the file will be stored with the component.
The Model Wizard has now created a VHDL model file that describes all the inputs and outputs, but has no actual behavior. It has also created a device symbol with entries linking to it to the file. We now have two steps left: first to fill in the actual behavior part of the VHDL model, and then to build a test circuit to make it work.
By now, you have learned the basic ideas about VHDL with LogicWorks, but there is much more to learn. This lab material is only an introduction to VHDL with LogicWorks 5. More about VHDL will be introduced in the future labs. There are some LogicWorks 5 manuals available. If you want to work through more tutorials in the manual or want to know more, you can ask me during the lab. You may also ask me questions at lab time or at my office hours in CL119. If a lab requires new features, I will explain more within the lab.
LogicWorks is a trademark of Capilano Computing.
Thursday, 11-Dec-2014 14:23:38 CST