CS301 Lab: Introduction to VHDL with LogicWorks 5

Objectives of this lab:


	To create VHDL Models with LogicWorks 5 and 
	verify the validity of boolean algebra.

Preparation


	Read lab lecture notes 
	which contains tutorials for creating VHDL Model using LogicWorks 5.

Lab Assignments

1. Build a 4-input majority detector device with a VHDL Model.

2. Create a VHDL Model for the following circuit.


Questions

Hand in the answers to these questions:


	1. What does VHDL stand for? 

	2. What are the two basic constructs required in every 
	   VHDL file?   Briefly describe each one.


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