CS301 Lab: Introduction to VHDL with LogicWorks 5

Objectives of this lab:

	To create VHDL Models with LogicWorks 5 and 
	verify the validity of boolean algebra.

Preparation

	Read lab lecture notes 
	which contains tutorials for creating VHDL Model using LogicWorks 5.

Lab Assignments

1. Build a 4-input majority detector device with a VHDL Model.

• A 4-input majority detector has the following property:
  The output is high if two or more of the inputs are high.
• Create a VHDL Model for a Device Symbol "majority4".
• Build a circuit using "majority4" and the other I/O devices
  in LogicWorks 5 to verify the truth table of the 4-input majority detector.

  Hand in the following:

• Print out of your VHDL Model file.
• Print out of the circuit testing the 4-input majority detector (show all 16 cases).
• Truth table of the circuit testing results.

2. Create a VHDL Model for the following circuit.

• Find out the Boolean expression of the circuit.
• Create a VHDL Model for the circuit.
• Compile the VHDL Model for the circuit.
• Use Run button to start the simulation.
• Use I/O Panel to check input and output values of the VHDL Model.
• Use Timing button to show the timing diagram.

  Hand in the following:

• Print out of your VHDL Model file.
• Find out the truth table of the VHDL Model.

Questions

Hand in the answers to these questions:

	1. What does VHDL stand for? 

	2. What are the two basic constructs required in every 
	   VHDL file?   Briefly describe each one.

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