CS301 Lab: Introduction to VHDL in Xilinx

Objectives of this lab:

	To create VHDL Model in Xilinx and simulate the Behavioral Model


	Read lab lecture notes 
	which contains material for creating VHDL Model in Xilinx.
	PCs with Xilinx ISE 10.1 and ISE Simulator are needed.
	Xilinx WebPack can be downloaded for free.

Lab Practice

Design a 4-bit up-down counter by using VHDL in Xilinx

Lab Assignments

Design a counter with more control signals by using VHDL in Xilinx

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