CS301 Lab: Introduction to VHDL in Xilinx

Objectives of this lab:

	To create VHDL Model in Xilinx and simulate the Behavioral Model

Preparation

	Read lab lecture notes 
	which contains material for creating VHDL Model in Xilinx.
	PCs with Xilinx ISE 10.1 and ISE Simulator are needed.
	Xilinx WebPack can be downloaded for free.

Lab Practice

Design a 4-bit up-down counter by using VHDL in Xilinx

• Create a project called Counter01 or whatever you like.
• Create VHDL source for a 4-bit up-down counter. You can name it counter or anything you prefer.
• Synthesize your code in the counter.vhd or whatever name you gave.
• Simulate the Module Using the ISE Simulator.
• Show your lab instructor the counter simulation results.

Lab Assignments

Design a counter with more control signals by using VHDL in Xilinx

• You will design an 8-bit counter with Load, Reset, and Increment options.
• Please note that the input ports will be Clock, Load, Reset, Increment and the load in value Din (8 bit), the output will be the counter output Cout (8 bit).

  Hand in:

• Your VHDL file code.
• Print out of the wave form simulation.

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Copyright: Department of Computer Science, University of Regina.