# CS301 Lab: VHDL Syntax for Port, Mode, and Type Signal Concurrency

## Objectives of this lab:

```
To learn more about VHDL Syntax.
To create VHDL Models with LogicWorks 5 and
build adders and subtractors circuits.

```

## Preparation

```
Read lab lecture notes.

```

## Lab Assignments

### A quick review:

• A half-adder has the following properties:
```
Truth Table
===========

x  y  s  c
----------
0  0  0  0
0  1  1  0
1  0  1  0
1  1  0  1
----------

Functions:
==========

s = x xor y
c = x and y

```
• A full-adder has the following properties:
```
Truth Table
===========

a  b  c  s   c2
----------------
0  0  0  0   0
0  0  1  1   0
0  1  0  1   0
0  1  1  0   1
1  0  0  1   0
1  0  1  0   1
1  1  0  0   1
1  1  1  1   1
----------------

Functions:
==========

s = a xor b xor c
c2 = (a and b) or (c and (a xor b))

```

### 1. Build a half-adder device with a VHDL Model.

• Create a VHDL Model for a Device Symbol "HalfAdder".
• Build a Half-Subtractor circuit using "HalfAdder" with additional "not" gates.
• Connect some I/O devices and verify the truth table of the Half-Subtractor.
• Build a Full-Adder circuit using "HalfAdder" with an additional "or" gate.
• Connect some I/O devices and verify the truth table of the Full-Adder.

Hand in the following:

• Print out of your VHDL Model file for the Half-Adder.
• Print out of the circuit of your Half-Subtractor and its truth table.
• Print out of the circuit of your Full-Adder made by using two HalfAdder devices and the truth table from your experiment.

### 2. Build a Full-Adder device with a VHDL Model.

• Create a VHDL Model for a Device Symbol "FullAdder".
• Build a Full-Subtractor circuit using the "FullAdder" device with two additional "not" gates.
• Connect some I/O devices and verify the truth table of the Full-Subtractor.

Hand in the following:

• Print out of your VHDL Model file.
• Print out of the circuit of your Full-Subtractor and its truth table.

### 3. Build an array of eight XOR gates device with a VHDL Model.

• Create a VHDL Model for a Device Symbol "xor_gate_8".
• Build a simple circuit using "xor_gate_8" with additional I/O devices and verify your "xor_gate_8".

Hand in the following:

• Print out of your VHDL Model file for the "xor_gate_8".
• Print out of the circuit using "xor_gate_8" in it.

### 4. Build an array of eight OR gates device with a VHDL Model.

Same requirements as part 3.

## Questions

```
1. What does a type mean in VHDL? Give an example.

```

 This page last modified: Tuesday, 11-Sep-2012 15:21:55 CST Accessed times. Copyright: Department of Computer Science, University of Regina.