CS301 Lab: VHDL Syntax for Port, Mode, and Type
Signal Concurrency

Objectives of this lab:


	To learn more about VHDL Syntax.
	To create VHDL Models with LogicWorks 5 and 
	build adders and subtractors circuits.

Preparation


	Read lab lecture notes. 

Lab Assignments

A quick review:

1. Build a half-adder device with a VHDL Model.

2. Build a Full-Adder device with a VHDL Model.

3. Build an array of eight XOR gates device with a VHDL Model.

4. Build an array of eight OR gates device with a VHDL Model.

Same requirements as part 3.

Questions


	1. What does a type mean in VHDL? Give an example.


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