We have examined some simple VHDL entities and design entry procedures. Now let's take a closer look at some of the rules and options available to us when we create a design in VHDL.
Here are some examples of valid and invalid names:
Valid names: decode8 just_in_time array_4 Invalid names: 8decide (begins with a digit) my design (space inside a name) signal (reserved word) your_words? (special character ? not allowed) _what_4 (begins with underscore) in__time (two consecutive underscores)Here is a list of some reserved words for your reference:
abs access after alias all and array assert attribute architecture begin block body buffer bus case constant component configuration downto disconnect else elsif end entity exit file for function group generic generate guarded if impure in inertial inout is label loop literal linkage library mod map nand new next nor not null of on open or others out port pure process package postponed procedure range record rem ror rol return reject report register select sla sll sra srl signal subtype severity shared then to type transport use until units unaffected variable wait when while with xnor xor
Example: y <= a and (not b);
Two consecutive hyphens are used to lead out the inline documentation/comment. A comment is explanatory text that is ignored by VHDL compiler.
Example: -- This is a comment in VHDL.
BUFFER is a special case of OUT, which allows the port value to be "updated" or "modified" by the CPLD logic and to be fed back into the CPLD logic to be used by another function.
The BIT type is native to VHDL and defined in the standard library of VHDL. BIT can have only two values:'0' and '1'. The values are placed in single quotes because VHDL treats them like ASCII characters.If we want to assign a multiple-bit number to a series of related input and output ports, we can use the type BIT_VECTOR.
For Example, define a 4-bit vector d: d: IN BIT_VECTOR (3 downto 0);Each of the elements of this vector can be individually addressed by indicating its position by a number in parentheses.
For the definition with range indication (3 downto 0), elements are: d(3), d(2), d(1), d(0); d(3) holds the most significant bit. For the definition with range indication (0 to 3), elements are: d(0), d(1), d(2), d(3); d(0) holds the most significant bit. VHDL always makes vector assignments from left to right. The contents of those vectors can be chosen by selecting how the elements are numbered.Constant values assigned to BIT_VECTORs are written in double quotes, because the VHDL compiler treats them
If a port d is defined by d: IN BIT_VECTOR (3 downto 0); then the following groups of the statements are equivalent. d(3) <= '0'; d <= "0101"; d(2) <= '1'; d(1) <= '0'; d(0) <= '1'; If a port d is defined by d: IN BIT_VECTOR (0 to 3); then the following groups of the statements are equivalent. d(0) <= '1'; d(1) <= '0'; d(2) <= '1'; d(3) <= '0'; d <= "1010";
'U' -- Uninitialized 'X' -- Forcing Unknown '0' -- Forcing 0 '1' -- Forcing 1 'Z' -- High Impedance 'W' -- Weak Unknown 'L' -- Weak 0 'H' -- Weak 1 '-' -- Don't careTo use STD_LOGIC in a VHDL file, you must include the following reference to the VHDL library called IEEE and the std_logic_1164 package before the entity declaration:
library IEEE; use IEEE.std_logic_1164.all;The std_logic_1164 package contains the type definitions of the STD_LOGIC types.
library IEEE; use IEEE.std_logic_1164.all; entity Four_and_array is port( a0 : in std_logic; a1 : in std_logic; a2 : in std_logic; a3 : in std_logic; b0 : in std_logic; b1 : in std_logic; b2 : in std_logic; b3 : in std_logic; c0 : out std_logic; c1 : out std_logic; c2 : out std_logic; c3 : out std_logic ); end Four_and_array; architecture arch1 of Four_and_array is begin -- Your VHDL code defining the model goes here c0 <= a0 and b0; c1 <= a1 and b1; c2 <= a2 and b2; c3 <= a3 and b3; end arch1;Now rewrite the VHDL file for the 4-bit AND array using STD_LOGIC_VECTOR types.
library IEEE; use IEEE.std_logic_1164.all; entity Four_and_vec is port( a : in std_logic_vector(0 to 3); b : in std_logic_vector(0 to 3); c : out std_logic_vector(0 to 3) ); end Four_and_vec; architecture arch1 of Four_and_vec is begin -- Your VHDL code defining the model goes here c <= a and b; end arch1;
The statements for the Boolean expressions are examples of concurrent signal assignment statements. The idea behind signal concurrency is that all concurrent statements are evaluated at the same time. (Concurrent means "simultaneous".)
In the other programming languages such as BASIC, c, or C++, the statements are executed in sequential order. However, for a hardware description language, signal concurrency does make sense since its purpose is to synthesize hardware rather than run a sequence of program statements.
Let's use half adder as an example,
Two signal bits a and b are added to produce the sum s and carry c. The circuit is defined by the two equations: s = a xor b and c = a and b. Suppose both inputs are 1, then carry is 1 and the sum bit is 0. Further suppose that input b is changed to a 0. Now the carry is 0 and the sum is 1.
Which changed first, sum or carry? Since both outputs depend on the same two inputs, both outputs ideally change at the same time. That is how the hardware behaves. In VHDL, we would write the following two statements:
s <= a xor b; c <= a and b;
Tuesday, 11-Sep-2012 15:20:28 CST