CS301 Lab: Using VHDL to Describe Adders

Objectives of this lab:


	To learn more about VHDL Syntax structures.
	To create VHDL Models with LogicWorks 5 and build 
	circuits to test your adders.

Preparation


	Read lab lecture notes. 

Lab Assignments

Build a 4-bit parallel adder/subtractor device with a VHDL Model.


Questions


	1.	How does a PROCESS work in VHDL?

	2.	Where do you make a COMPONENT declaration?


This page last modified:
Monday, 15-Oct-2012 15:29:02 CST
Accessed     times.


Copyright: Department of Computer Science, University of Regina.