CS301 Lab: Using VHDL to Describe Adders

Objectives of this lab:

	To learn more about VHDL Syntax structures.
	To create VHDL Models with LogicWorks 5 and build 
	circuits to test your adders.


	Read lab lecture notes. 

Lab Assignments

Build a 4-bit parallel adder/subtractor device with a VHDL Model.


	1.	How does a PROCESS work in VHDL?

	2.	Where do you make a COMPONENT declaration?

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