CS301 Lab: Using VHDL to Describe Adders
Objectives of this lab:
To learn more about VHDL Syntax structures.
To create VHDL Models with LogicWorks 5 and build
circuits to test your adders.
Read lab lecture notes.
Build a 4-bit parallel adder/subtractor device with a VHDL Model.
Here is a 4-bit Parallel 2's Complement Adder/Subtractor Design:
For the 4-bit binary numbers A = A4A3A2A1 and D=D4D3D2D1 ,
assume that they are in the 2's complement representation.
This design implements addition A + D
when the control signal sub inputs 0.
This design implements subtraction A - D
when the control signal sub inputs 1.
The 4-bit vector S = S4S3S2S1 will hold the results.
Create a VHDL Model for a Device Symbol "add_sub".
Build a simple circuit by connecting some I/O devices
and verify the operation of your 4-bit parallel adder/subtractor.
Hand in the following:
Print out of your VHDL Model file for the 4-bit parallel adder/subtractor.
Print out of your VHDL Model file for the full adder component.
Print out of the circuits with the newly created device
4-bit parallel adder/subtractor testing the following operations:
5 + 2 = ?
9 - 6 = ?
F - 8 = ?
6 - 9 = ?
1. How does a PROCESS work in VHDL?
2. Where do you make a COMPONENT declaration?
This page last modified:
Monday, 15-Oct-2012 15:29:02 CST
Copyright: Department of Computer Science, University of Regina.