Using VHDL to Describe Counters

Objectives of this lab:


	To learn more about VHDL Syntax structures.
	To create VHDL Models for counters with LogicWorks 5.

Preparation


	Read lab lecture notes. 

Lab Assignments

1. Build a 4-bit UP-DOWN counter device with a VHDL Model.

2. Build a counter device with a VHDL Model to simulate a regular clock face.

3. Build a 3-bit counter device with a VHDL Model.


Questions


	1.	What is the Modulus of a counter?
	2.	What does a Modulo-12 counter mean?


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Copyright: Department of Computer Science, University of Regina.