~ftp/pub/class/400f/8bitcpu.cct
- there is now a 256 x 8 bit memory attached to the bus through a Memory Address Register(MAR)
- there is now a Program Counter(PC) with a built in increment by one function.
- the ALU has been expanded to perform the invert operation on the Accumulator(ACC)
- all the switches have been grouped into one area to simulate a control unit.
To get a feel for the circuit before more details are examined,
do the following:
1. load the number 8 into memory location 2
2. move (the contents in) memory location 2 to the PC
3. increment the PC
Write down the signals you used:
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- Because the memory has 8 bits we can have an 8 bit opcode.
The format of the instruction for this experiment is:
- The source and destination addresses are further divided as follows:
- Two bits are assigned for the addressing mode and one bit is
specified for selecting register B or C(B=0, C=1) if the addressing
mode is register.
The following table summarizes the addressing modes for this CPU:
Mode Mode Description =========================== 00 Register, e.g. B --------------------------- 01 Immediate, e.g. #n --------------------------- 10 indirect, e.g. (B) --------------------------- 11 absolute, e.g. n ---------------------------
For the purposes of the lab, this CPU has only three instructions:opcode# MNEMONIC DESCRIPTION ============================================================== 10 NOT source,destination invert the contents of source and store the result in destination -------------------------------------------------------------- 00 XOR source,destination XOR the contents of source, destination, and store the result in the destination -------------------------------------------------------------- 01 AND source,destination AND the contents of source, destination, and store the result in the destination --------------------------------------------------------------
- The following are valid assembly language instructions:
1) NOT 2,B ; NOT memory location 2 and store the result in register B. The machine lauguage code for it is as follows: 10110000 00000010 2) XOR #5,(C) ; XOR 5 and the contents of the memory location stored in C and store the result in the memory location stored in C. The machine lauguage code for it is as follows: 00010101 00000101
- Microinstructions
Fetch Cycle Before an opcode can be interpreted it must be loaded into the IR. With our circuit this can be done with the following microcode: t1: PCout, MARin. ; set up memory address t2: MEMout, MEMenable, IRin.;fetch opcode and store in IR t3: PC+1out,PCin. ;increment PC
Indirect Cycle Once an opcode is fetched any operands must be fetched. The NOT operation, for example, has two operands: the source and the destination. The type of fetch will depend on the addressing mode used. The following microinstructions can be used to fetch the operand for immediate addressing. t1: PCout, MARin. ;set up to fetch operands address t2: MEMout, MEMenable, ACCin. ;move operand to ACC t3: PC+1out, PCin. ;increment PC The first operand is loaded into the accumulator(ACC). The second operand would be loaded into the TEMP register. An example for absolute addressing mode is: t1: PCout, MARin. ;set up to fetch operands address t2: MEMout, MEMenable, TEMPin. ;move operand address to TEMP t3: PC+1out, PCin. ;increment PC t4: TEMPout, MARin. ;prepare to get operand t5: MEMout, MEMenable, TEMPin. ;get operand The indirect cycle for register mode and indirect mode have not been shown but the reader should be able to see how they could be implemented.
Execute Cycle The execute cycle is different for each opcode the CPU can execute. For the NOT operation the following microinstructions do the job for indirect and absolute addressing.(these assume the fetch and indirect cycles have been completed so that the ACC is set up). NOT t1: ALUout, MEMin, MEMenable. ;store result in destination. Note that ; the MAR still contains the destination ; address from the indirect cycle
Given the following program stored in memory write out the equivalent
assembly language mnemonics:
Location Contents Assembly Language Mnemonics
=============================================================
0 10000001
-------------------------------------------------------------
1 00010110
-------------------------------------------------------------
2 00000101
-------------------------------------------------------------
3 00001000
-------------------------------------------------------------
Pre-load the value 1 in the B register, preload 0 in
the memery location 8,
and then load the preceding program (in machine code) to the memory.
Make sure the PC points to the start of the program.
Write out the microinstructions necessary to execute the program.
Execute the program.
Copyright: Department of Computer Science, University of Regina.