Learn an 8-Bit CPU

1. Purpose

CPU is the most important part of a computer. It is controlled by a series of small operations called micro-operations. You have got a feel in the last lab with a one-bit CPU and a two-bit CPU. In this lab, we will look at an 8-bit CPU.

2. Introduction to the 8-bit CPU

The 8-bit CPU can be obtained by copying the following file to your directory:
~ftp/pub/class/301/ftp/8bitcpu.cct.
This circuit is simply an extension of what you have already done in the last lab.
Notice the similarities such as temp, accumulator, IR, B and C registers, and the external input.
Notice the differences:
The memory has a memory address register.
There is a decoder associated with the ALU.
There is a Program Counter (PC).
There is an adder to produce PC+1.

Machine Instructions for the 8-bit CPU

Because the memory has 8-bit we can have an 8-bit instruction.
The format of the instruction for this experiment is:
The source and destination addresses are further divided as follows:

Two bits are assigned for the addressing mode and one bit is specified
for selecting register B or C(B=0, C=1) if the addressing mode is register.

Our 8-bit CPU only has the following three operations defined so far:


        opcode# MNEMONIC                DESCRIPTION
        ==============================================================
        10      NOT source, destination  invert the contents of
                                         source and store the result
                                         in destination
        --------------------------------------------------------------
        00      XOR source, destination  XOR the contents of source,
                                         destination, and store the
                                         result in the destination
        --------------------------------------------------------------
        01      AND source, destination  AND the contents of source,
                                         destination, and store the
                                         result in the destination
        --------------------------------------------------------------

The following table summarizes the addressing modes for this CPU:

	 
        Mode    Mode Description
        ===========================
        00      Register, e.g. B
        ---------------------------
        01      Immediate, e.g. #n
        ---------------------------
        10      indirect, e.g. (B)
        ---------------------------
        11      absolute, e.g. n
        ---------------------------

The following examples show you the valid assembly language instructions:


        1) NOT 2,B ; NOT memory location 2 and store the result in
        register B. The machine language code for it is as follows:

        10110000
        00000010

        2) XOR #5,(C) ; XOR 5 and the contents of the memory location
        stored in C and store the result in the memory location
        stored in C. The machine language code for it is as follows:

        00010101
        00000101

Microinstructions for the 8-bit CPU


        Fetch Cycle

        Before an opcode can be interpreted it must be loaded into
        the IR. With our circuit this can be done with the following
        microcode:


            t1: PCout, MARin. ; set up memory address

            t2: MEMenable, MEMout, IRin.;fetch opcode and store in IR

            t3: PC+1out,PCin. ;increment PC


        Indirect Cycle

        Once an opcode is fetched any operands must be fetched.
        The NOT operation, for example, has two operands:
        the source and the destination.

        The type of fetch will depend on the addressing mode used.
        The following microinstructions can be used to fetch the
        operand for immediate addressing.



            t1: PCout, MARin. ;set up to fetch operands address

            t2: MEMenable, MEMout, ACCin. ;move operand to ACC

            t3: PC+1out, PCin. ;increment PC



        The first operand is loaded into the accumulator(ACC).
        The second operand would be loaded into the TEMP register.
        An example for absolute addressing mode is:



            t1: PCout, MARin. ;set up to fetch operands address

            t2: MEMenable, MEMout, TEMPin.  ;move operand address to TEMP

            t3: PC+1out, PCin. ;increment PC

            t4: TEMPout, MARin. ;prepare to get operand

            t5: MEMenable, MEMout, TEMPin. ;get operand



        The indirect cycle for register mode and indirect mode
        have not been shown but the reader should be able to see
        how they could be implemented.


        Execute Cycle

        Where the results are stored is different for each 
        opcode the CPU can execute. When the destination's 
        "mode" is indirect or absolute (for example, the 
        XOR from above), the results are stored in memory.
        The following microinstructions are used:

        t1: ALUout, MEMenable, MEMin. ;store result in destination.

        Note that:
        MAR is assumed to contain the destination address

3. More Explanations on addressing Modes

The difference between absolute vs immediate addressing:

In absolute addressing, the operand is located in the address specified in the instruction.
For example: NOT 2,B means NOT (or invert) the contents of location 2, and save it in register B.
In immediate addressing, the operand is specified in the instruction.
For example: AND #2,B means AND the value 2, with register B and save the result in B.

4. CONCLUSION

 
Many devices may be connected to a common bus by using tri-state buffers.

5. Lab Assignments

Copyright: Department of Computer Science, University of Regina.