CS301 Lab: Using VHDL to Describe
a 3-8 Decoder and a 7-segment Display

Objectives of this lab:

	To learn more about VHDL Syntax structures.
	To create VHDL Models with LogicWorks 5 and build 
	circuits to test your 3-8 decoder and 7-segment display.

Preparation

	Read lab lecture notes. 

Lab Assignments

1. Build a 3-8 decoder device with a VHDL Model.

• Create a VHDL Model for a Device Symbol "decoder38v1" with a control signal.
• Build a simple circuit by connecting some I/O devices and verify the truth table of the 3-8 decoder.

  Hand in the following:

• Truth table of the 3->8 decoder with an enable signal.
• Print out of your VHDL Model file for the 3->8 decoder.
• Print out of the circuit with the newly created device of 3->8 decoder used to test its truth table.

2. Build a 7-segment display device with a VHDL Model.

• Create a VHDL Model for a Device Symbol "display7v1".
• When the inputs are from 0 to 9, the device should be able to display the digit; otherwise, do not show anything.
• Build a simple circuit by connecting some I/O devices such as hex keyboard and a 7-segment display device
  to verify the output of your circuits.

  Hand in the following:

• Truth table of the 7-segment display device.
• Print out of your VHDL Model file for the 7-segment display device.
• Print out of the circuit with the newly created device of 7-segment display used to demonstrate its output.

Questions

	1. What is the hardware equivalent of a signal in a VHDL file? 

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Copyright: Department of Computer Science, University of Regina.