CS301 Lab: Using VHDL to Describe
a 3-8 Decoder and a 7-segment Display

Objectives of this lab:


	To learn more about VHDL Syntax structures.
	To create VHDL Models with LogicWorks 5 and build 
	circuits to test your 3-8 decoder and 7-segment display.

Preparation


	Read lab lecture notes. 

Lab Assignments

1. Build a 3-8 decoder device with a VHDL Model.

2. Build a 7-segment display device with a VHDL Model.


	


Questions


	1. What is the hardware equivalent of a signal in a VHDL file? 


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