We have examined some simple VHDL entities and design entry procedures. We also learned the concurrent signal assignment statements and some of the rules and options available to us when we create a design in VHDL. In this lab, let's learn a new statement in making VHDL files.
WITH __expression SELECT __signal <= __expression WHEN __constant_value, __expression WHEN __constant_value, __expression WHEN __constant_value, __expression WHEN __constant_value;This type of statement can be used to encode an SOP Boolean expression, as represented by a truth table.
For example, if we know that a circuit has the following truth table:
D2 D1 D0 Y -------------- 0 0 0 0 0 0 1 0 0 1 0 1 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 --------------we can represent the corresponding expression in VHDL as follows, assuming we have defined d as type BIT_VECTOR(2 downto 0):
WITH d SELECT y <= '1' WHEN "010", '1' WHEN "111", '0' WHEN others;This statement can be interpreted as saying, "when the value of d is either "010" or "111", the output y is set to '1'.
Using LogicWorks to create a VHDL file for the above example, we can obtain the following:
library IEEE; use IEEE.std_logic_1164.all; entity Ex250 is port( d : in std_logic_vector(2 downto 0); y : out std_logic ); end Ex250; architecture arch1 of Ex250 is begin -- Your VHDL code defining the model goes here WITH d SELECT y <= '1' WHEN "010", '1' WHEN "111", '0' WHEN others; end arch1;We can see the simulation through I/O Panel or Circuits window.
For example, a 3-bit input port can be specified by either of the following two ways:
d: IN BIT_VECTOR(2 downto 0); d: IN INTEGER RANGE 0 to 7;
D2 D1 D0 Y -------------- 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 0 --------------Here is the VHDL code to describe the operation of the circuit.
library IEEE; use IEEE.std_logic_1164.all; entity EX253 is port( D : in std_logic_vector (2 downto 0); Y : out std_logic ); end EX253; architecture arch1 of EX253 is begin -- Your VHDL code defining the model goes here with d select y <= '1' when "001", '1' when "101", '1' when "110", '0' when others; end arch1;Here is the VHDL code with d specified as type INTEGER.
library IEEE; use IEEE.std_logic_1164.all; entity EX254 is port( D : in integer range 0 to 7; Y : out std_logic ); end EX254; architecture arch1 of EX254 is begin -- Your VHDL code defining the model goes here with d select y <= '1' when 1, '1' when 5, '1' when 6, '0' when others; end arch1; -- Note that the output, y, is of type STD_LOGIC. -- It is assigned constant value in single quotes. -- The values of d is of type INTEGER. -- They are specified without quotes.
A B C W X Y Z --------------- 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 1 0 0 1 1 0 0 1 1 1 0 0 1 1 0 0 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 0 1 1 1 1 0 0 1 0 ---------------The Boolean expressions can be easily obtained by using K-map. Although we can use concurrent signal assignment statements for the four outputs, with the truth table above, selected signal assignment statements may come handier. To explore more about selected signal assignment statements, we are going to use it for this example. We need a signal name for inputs and a signal name for outputs. These names can represent multi-bit objects of type BIT_VECTOR, STD_LOGIC_VECTOR. or INTEGER, but they must still have only one name. For example, the following statement is wrong:
-- Illegal syntax WITH a, b, c, SELECT w, x, y, z <= "1000" WHEN "000", etc.To use selected signal assignment statement, we can create a signal that bundles together the inputs into a single group of type BIT_VECTOR, STD_LOGIC_VECTOR. or INTEGER. We also need a multi-bit signal for all outputs that we can use in a selected signal assignment statement and "peel off" the various bits and map them to single-bit outputs.
A signal is a VHDL construct used for connecting internal parts of a design, something like a internal connecting wire. The following diagram shows the general idea. Ports A, B, and C come into the entity as separate ports. Inside the design they are bundled together like a 3-wire cable in the signal called inputs. (Note: "inputs" here is a user defined name; it could be any name at all, as long as it conforms to the rules for valid VHDL names. "inputs" is chosen because it is descriptive of the function and easy to type.)
To bundle the ports together, we can concatenate, or link, the ports together using the & operator. The VHDL statement is
inputs <= a & b & c;This has the effect of mapping the input ports to the internal signal in the correct order.
Input Ports Mapped to a 3-Bit Signal "inputs" inputs(2) inputs(1) inputs(0) ----------------------------------------- a b cWe can also achieve the same thing by individually mapping the input ports to the internal signal one bit at a time,
inputs(2) <= a; inputs(1) <= b; inputs(0) <= c;Similarly, we can get the following for the output:
w <= outputs(3); x <= outputs(2); y <= outputs(1); z <= outputs(0);
Signal "outputs" Mapped to Output Ports outputs(3) outputs(2) outputs(1) outputs(0) ---------------------------------------------------------- w x y zThe complete VHDL file for the circuit in this example is given below.
library IEEE; use IEEE.std_logic_1164.all; entity Ex256 is port( a : in std_logic; b : in std_logic; c : in std_logic; w : out std_logic; x : out std_logic; y : out std_logic; z : out std_logic ); end Ex256; architecture arch1 of Ex256 is -- Declare signals signal inputs : STD_LOGIC_VECTOR(2 downto 0); signal outputs : STD_LOGIC_VECTOR(3 downto 0); begin -- Your VHDL code defining the model goes here inputs <= a & b & c; with inputs select outputs <= "1000" when "000", "0100" when "001", "0110" when "010", "1001" when "011", "0110" when "100", "0001" when "101", "1001" when "110", "0010" when "111", "0000" when others; w <= outputs(3); x <= outputs(2); y <= outputs(1); z <= outputs(0); end arch1;
The corresponding Boolean expression can be written in
Y = ((not A) and B) or (A and (not B)) or ((not C) and D)or
Y = (A xor B) or ((not C) and D)The output of the top OR gate does not feed an output port pin and is thus entirely internal to the design. We can represent the connection between the OR gates as a signal. We can call it a_xor_b. A VHDL file that implements this circuit is as follows:
library IEEE; use IEEE.std_logic_1164.all; entity Signal_Ex258 is port( a : in std_logic; b : in std_logic; c : in std_logic; d : in std_logic; y : out std_logic; ); end Signal_Ex258; architecture arch1 of Signal_Ex258 is -- Declare signal signal a_xor_b : STD_LOGIC; begin -- Define signal in terms of ports a and b a_xor_b <= ((not A) and B) or (A and (not B)); -- Combine signal with ports c and d y <= a_xor_b or ((not C) and D); end arch1;
For example, suppose we have a 3-bit port defined by
d: IN STD_LOGIC_VECTOR(2 downto 0);and a single-bit port defined by
enable: IN STD_LOGIC;We can combine the ports into signal by
signal inputs: STD_LOGIC_VECTOR(3 downto 0);
inputs <= enable & d;The above is equivalent to the following four statements:
inputs(3) <= enable; inputs(2) <= d(2); inputs(1) <= d(1); inputs(0) <= d(0);Another way to write the following statements would be:
inputs(3) <= enable; inputs(2 downto 0) <= d;Note: VHDL assigns elements of a vector from left-to-right. Therefore, d is assigned to inputs in the correct order.
Friday, 21-Aug-2020 15:22:26 CST |
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