Questions

1. What does SOP stand for?
2. Write the SOP form as a formula and in VHDL code based on the following truth table. (Use std_logic*, select statements, and port declaration)

   D2 D1 D0	Y
   0    0    0	1
   0    0    1	0
   0    1    0	0
   0    1    1	1
   1    0    0	0
   1    0    1	1
   1    1    0	0
   1    1    1	0

3. Write the following BIT_VECTOR statement using INTEGER type:

    d: IN BIT_VECTOR (3 downto 0); 

4. Using the truth table above, write the INTEGER equivalent of the select statement.
5. Can you write the following select statement. Why? Why not?

    WITH d2, d1, d0 SELECT
         y, y0 <= "11" when "010",
                  "00" when others; 

6. Where does a signal statement go in VHDL code?
7. How would we declare and use an input signal called temp1 to assign it three std_logic input values (d2,d1,and d0)? (two statements only)
8. What are two reasons for using signal statements?

Review

1. What is a decoder?
2. What is a 7 segment display?

Extra

1. If you have a .dwv file (VHDL code), how can you generate an associated part?