VHDL Design for an 8-bit RISC Computer CPU Controller
The following code is from "Digital Design with CPLD Applications and VHDL",
by Robert K. Dueck.
The idea here is to let you see the the CPU controller
can be designed by using a Finite State Machine.
Read the code, and have fun! If you are interested, you can read Chaper 14 of the book.
-----------------------------------------------------------------------------
-- Controller for 8-bit RISC CPU
-- Generates signals to transfer data between CPU modules
-- and controls arithmetic/logic functions.
-- Version 1 has four instructions, indicated in hexadecimal:
--
-- 1 ADD (Adds contents of Accumulator and MDR)
-- 8 LOAD (Loads data from ROM to Accumulator)
-- 9 OUTPUT (Transfers accumulator contents to Output Register)
-- F HALT (Stops processing)
--
-- Opcodes 0 to 7 are reserved for ALU functions, as follows:
--
-- 0 INC (Increments Accumulator (ACC))
-- 1 ADD (Adds contents of ACC and MDR)
-- 2 SUB (Subtracts contents of MDR from ACC)
-- 3 DEC (Decrements ACC)
-- 4 NOT (Complements ACC)
-- 5 AND (ACC AND MDR)
-- 6 OR (ACC OR MDR)
-- 7 XOR (ACC XOR MDR)
--
-- Above codes the same for opcodes and ALU function select codes.
--
-- Use BIT types so that control word can be assigned as hexadecimal.
ENTITY controller_v1 IS
PORT(
clock, reset : IN BIT;
instruction : IN BIT_VECTOR(3 downto 0);
fetch, pc_inc, pc_oe : OUT BIT;
ir_ld, ir_oe, mar_ld, rom_oe : OUT BIT;
acc_ld, acc_oe, alu_oe, mdr_ld : OUT BIT;
or_ld : OUT BIT;
s : OUT BIT_VECTOR(2 downto 0));
END controller_v1;
ARCHITECTURE ctrl OF controller_v1 IS
TYPE state_type IS (start, fetch1, fetch2, fetch3, fetch4, fetch5,
load1, load2, load3, load4,
add1, add2, add3, add4, add5, add6,
output1, output2, halt);
SIGNAL state : state_type;
SIGNAL control_word : BIT_VECTOR(15 downto 0);
BEGIN
PROCESS(clock, reset)
BEGIN
IF(reset = '0')THEN
state <= start;
ELSIF(clock'EVENT and clock = '1')THEN
-- Create state machine for instruction sequences.
CASE state IS
WHEN start =>
state <= fetch1;
WHEN fetch1 => -- Fetch cycle
state <= fetch2;
-- (same for all instructions)
WHEN fetch2 =>
state <= fetch3;
WHEN fetch3 =>
state <= fetch4;
WHEN fetch4 =>
state <= fetch5;
WHEN fetch5 =>
CASE instruction IS
-- Decode instruction
WHEN x"1" =>
state <= add1;
WHEN x"8" =>
state <= load1;
WHEN x"9" =>
state <= output1;
WHEN x"F" =>
state <= halt;
WHEN others =>
state <= halt;
END CASE;
WHEN add1 => -- ADD
state <= add2;
WHEN add2 =>
state <= add3;
WHEN add3 =>
state <= add4;
WHEN add4 =>
state <= add5;
WHEN add5 =>
state <= add6;
WHEN add6 =>
state <= fetch1;
WHEN load1 => -- LOAD
state <= load2;
WHEN load2 =>
state <= load3;
WHEN load3 =>
state <= load4;
WHEN load4 =>
state <= fetch1;
WHEN output1 => -- OUTPUT
state <= output2;
WHEN output2 =>
state <= fetch1;
WHEN halt => -- HALT
state <= halt;
WHEN others =>
state <= halt;
END CASE;
END IF;
END PROCESS;
-- Assign control bus outputs.
fetch <= control_word(14);
pc_inc <= control_word(13);
pc_oe <= control_word(12);
ir_ld <= control_word(11);
ir_oe <= control_word(10);
mar_ld <= control_word(9);
rom_oe <= control_word(8);
acc_ld <= control_word(7);
acc_oe <= control_word(6);
alu_oe <= control_word(5);
mdr_ld <= control_word(4);
or_ld <= control_word(3);
s <= control_word(2 downto 0);
-- Assign output control lines for each control state
-- "Fetch" output goes LOW to turn on LED during fetch cycle
WITH state SELECT
control_word <= x"4000" WHEN start, -- Fetch LED OFF
x"1000" WHEN fetch1, -- pc_oe
x"2200" WHEN fetch2, -- pc_inc, mar_ld
x"0100" WHEN fetch3, -- rom_oe
x"0800" WHEN fetch4, -- ir_ld
x"0000" WHEN fetch5, -- wait state
x"4400" WHEN load1, -- ir_oe
x"4200" WHEN load2, -- mar_ld
x"4100" WHEN load3, -- rom_oe
x"4080" WHEN load4, -- acc_ld
x"4401" WHEN add1, -- ir_oe, s=001
x"4201" WHEN add2, -- mar_ld, s=001
x"4101" WHEN add3, -- rom_oe, s=001
x"4011" WHEN add4, -- mdr_ld, s=001
x"4021" WHEN add5, -- alu_oe, s=001
x"4081" WHEN add6, -- acc_ld, s=001
x"4040" WHEN output1, -- acc_oe
x"4008" WHEN output2, -- or_ld
x"4000" WHEN others; -- Fetch LED stays OFF
END ctrl;