VHDL Design for a Counter with Load, Rest, and Increment controls

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-- Company: 	   Computer Science Department 
-- Engineer: 	   Guili Liu
-- 
-- Create Date:    13:38:50 10/16/2009 
-- Design Name:    counter.vhd
-- Module Name:    counter - Behavioral 
-- Project Name:   counter
-- Target Devices: xc2vp30-6ff1152
-- Tool versions: 
-- Description:    This is the top level HDL file for a counter with load,
-- 		   rest, and increment controls.
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity counter is
      port(
         CLK : in std_logic;     -- clock signal to run system
         Din: in std_logic_vector (7 downto 0); -- input data to load into counter
         Rst: in std_logic;      -- external reset to reset counter to zero
         Load: in std_logic;     -- Load counter with Din input
         Inc: in std_logic;      -- Increment the counter
         Count: out std_logic_vector (7 downto 0);   -- output of counter  
         Carry: out std_logic    -- counter is FF and ready to wrap to zero
         );
end counter;
                
architecture Behavioural of Counter is
                
-- Can't use Count inside, need an intermediate value
signal Internal_Count: std_logic_vector(7  downto 0);  
begin
         reg_8Bit_Counter: process ( CLK)
                begin
                    if CLK'Event and CLK = '1' then
                       if Rst = '1' then
                           Internal_Count <= "00000000";
                       elsif Load = '1' then
                           Internal_Count <= Din;
                       elsif Inc = '1' then
                           Internal_Count<= Internal_Count + 1;
                       end if;
                    end if;
                end process reg_8Bit_Counter;
                    
         combo_counter: process ( Internal_Count)
                begin
                    if Internal_Count = "11111111" then
                        Carry <= '1';
                    else
                        Carry <= '0';
                    end if;
                        Count <= Internal_Count;
                end process combo_counter;

end Behavioral;