VHDL Design for a Counter with a Finite Sate Machine
VHDL Code for the Finite State Machine
----------------------------------------------------------------------------------
-- Company: Computer Science Department
-- Engineer: Guili Liu
--
-- Create Date: 10:30:58 02/31/2009
-- Design Name: counter.vhd
-- Module Name: counter - Behavioral
-- Project Name: counter
-- Target Devices: xc2vp30-6ff1152
-- Tool versions:
-- Description: This is the top level HDL file for a counter with finite states
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Vhdl_FSM is
port(CLK : in std_logic; -- clock signal to run system
EXT_RST: in std_logic; -- external reset to control restarting FSM
LSB_BIT: in std_logic; -- input to control FSM
Cntl_Shft: out std_logic; -- output to control shift of register
Cntl_Write: out std_logic; -- output to allow register to load
-- to allow us to see internal signals on simulator
Done: out std_logic;
Inc: out std_logic;
NState: out std_logic_vector (1 downto 0)
);
end Vhdl_FSM;
------------------------------------------------------------------------------
architecture RTL of Vhdl_FSM is
constant S0 : Std_logic_vector ( 1 downto 0) := "00";
constant S1 : Std_logic_vector ( 1 downto 0) := "01";
constant S2 : Std_logic_vector ( 1 downto 0) := "10";
constant S3 : Std_logic_vector ( 1 downto 0) := "11";
signal FSM_INC_3Bit : std_logic; -- if bit is high then increment 3bit counter
signal FSM_State: std_logic_vector ( 1 downto 0);
signal FSM_NextState: std_logic_vector (1 downto 0);
signal FSM_3BitCntr: std_logic_vector (2 downto 0); -- allows count upto 8
signal FSM_Done: std_logic; -- when the 8 steps are complete
begin
------------------------------------------------------------------------------
reg_3Bit_Counter: process (CLK)
begin
If CLK'Event and CLK = '1' then
If Ext_Rst = '1' then
FSM_3BitCntr <= "000";
elsif FSM_INC_3Bit = '1' then
FSM_3BitCntr <= FSM_3BitCntr + 1;
end if;
end if;
end process reg_3Bit_Counter;
------------------------------------------------------------------------------
reg_2Bit_FSM: process(CLK)
begin
If CLK'Event and CLK = '1' then
if Ext_Rst = '1' then
FSM_STATE <= "00";
else
FSM_STATE <= FSM_NextState;
end if;
end if;
end process reg_2Bit_FSM;
------------------------------------------------------------------------------
combo_Control_Outputs: process ( FSM_STATE)
begin
CASE FSM_STATE IS
WHEN S0 =>
Cntl_Shft <= '0';
Cntl_Write <= '0';
FSM_INC_3Bit <= '0';
WHEN S1 =>
Cntl_Shft <= '0' ;
Cntl_Write <= '1' ;
FSM_INC_3Bit <= '0' ;
WHEN S2 =>
Cntl_Shft <= '1' ;
Cntl_Write <= '0' ;
FSM_INC_3Bit <= '1' ;
WHEN S3 =>
Cntl_Shft <= '0' ;
Cntl_Write <= '0' ;
FSM_INC_3Bit <= '0' ;
WHEN others =>
Cntl_Shft <= '0' ;
Cntl_Write <= '0' ;
FSM_INC_3Bit <= '0' ;
END CASE;
end process combo_Control_Outputs;
------------------------------------------------------------------------------
combo_Next_state: process ( FSM_STATE, LSB_BIT, FSM_Done)
begin
case FSM_STATE is
when S0 =>
If LSB_BIT = '1' then
FSM_NextState <= S1;
else
FSM_NextState <= S2;
end if;
when S1 =>
FSM_NextState <= S2;
when S2 =>
FSM_NextState <= S3;
when S3 =>
if FSM_Done = '1' then
FSM_NextState <= S3;
else
FSM_NextState <= S0;
end if;
when others =>
FSM_NextState <= S0;
end case;
end process combo_Next_State;
------------------------------------------------------------------------------
combo_Done_Bit: process ( FSM_3BitCntr )
begin
if FSM_3BitCntr = "111" then
FSM_Done <= '1';
else
FSM_Done <= '0';
end if;
end process combo_Done_Bit;
------------------------------------------------------------------------------
-- This may not even be needed with the new simulator
-- not sure how to do this so just added these output signals
-- so we can see them on the simulator
combo_output_values: process ( FSM_3BitCntr )
begin
Done <= FSM_Done;
Inc <= FSM_INC_3Bit;
NState <= FSM_NextState;
end process combo_output_values;
end RTL;
State Diagram of the Finite State Machine