VHDL Design for a Pipelined 4-bit Multiplication
RTL Block Diagram of the Design
VHDL Code of the Design
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-- Company: CS
-- Engineer: Guili Liu
--
-- Create Date: 11:02:15 03/11/2009
-- Design Name:
-- Module Name: mult4p - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: Pipelined 4bit x 4bit multiply
-- It will create a sequential system which multiplies
-- a sequence of two 4bit 2's complement integers and
-- produces a sequence of 8bit 2's complement results.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
---- library UNISIM;
---- use UNISIM.VComponents.all;
entity mult4p is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
clk : in STD_LOGIC;
reset: in STD_LOGIC;
Pout : out STD_LOGIC_VECTOR (7 downto 0));
end mult4p;
architecture Behavioral of mult4p is
signal A_out: STD_LOGIC_VECTOR (3 downto 0);
signal B_out: STD_LOGIC_VECTOR (3 downto 0);
signal s0_in: STD_LOGIC;
signal s0_out: STD_LOGIC;
signal s1_out: STD_LOGIC;
signal s2_out: STD_LOGIC;
signal s3_out: STD_LOGIC;
signal A0_in: STD_LOGIC_VECTOR (3 downto 0);
signal A0_out: STD_LOGIC_VECTOR (3 downto 0);
signal A1_out: STD_LOGIC_VECTOR (3 downto 0);
signal A2_out: STD_LOGIC_VECTOR (3 downto 0);
signal A3_out: STD_LOGIC_VECTOR (3 downto 0);
signal B0_in: STD_LOGIC_VECTOR (3 downto 0);
signal B0_out: STD_LOGIC_VECTOR (3 downto 0);
signal B1_out: STD_LOGIC_VECTOR (2 downto 0);
signal B2_out: STD_LOGIC_VECTOR (1 downto 0);
signal B3_out: STD_LOGIC;
signal P0_in: STD_LOGIC_VECTOR (7 downto 0);
signal P0_out: STD_LOGIC_VECTOR (7 downto 0);
signal P1_in: STD_LOGIC_VECTOR (7 downto 0);
signal P1_out: STD_LOGIC_VECTOR (7 downto 0);
signal P2_in: STD_LOGIC_VECTOR (7 downto 0);
signal P2_out: STD_LOGIC_VECTOR (7 downto 0);
signal P3_in: STD_LOGIC_VECTOR (7 downto 0);
signal P3_out: STD_LOGIC_VECTOR (7 downto 0);
signal Pp3_out: STD_LOGIC_VECTOR (7 downto 0);
begin
-- input register A_reg
A_reg: Process (A, clk, reset)
begin
if reset = '1' then
A_out <= (others => '0');
elsif clk'event and clk = '1' then
A_out <= A;
end if;
end process A_reg;
-- input Register B_reg
B_reg: Process (B, clk, reset)
begin
if reset = '1' then
B_out <= (others => '0');
elsif clk'event and clk = '1' then
B_out <= B;
end if;
end process B_reg;
-- combo for sign value, A0reg and B0reg registers
process (A_out, B_out)
begin
S0_in <= A_out(3) XOR B_out(3);
-- get absolute value of A
if A_out(3) = '0' then
A0_in <= A_out;
else
A0_in <= not(A_out) + 1;
end if;
-- get absolute value of B
if B_out(3) = '0' then
B0_in <= B_out;
else
B0_in <= not(B_out) + 1;
end if;
end process;
-- Sign register S0_reg
S0reg: process(clk, reset, S0_in)
begin
if reset = '1' then
S0_out <= '0';
elsif clk'event and clk = '1' then
S0_out <= S0_in;
end if;
end process S0reg;
-- A0 register
A0reg: Process (reset, clk, A0_in)
begin
if reset = '1' then
A0_out <= "0000";
elsif (clk'event and clk = '1') then
A0_out <= A0_in;
end if;
end process A0reg;
-- B0 register
B0reg: Process (reset, clk, B0_in)
begin
if reset = '1' then
B0_out <= "0000";
elsif (clk'event and clk = '1') then
B0_out <= B0_in;
end if;
end process B0reg;
-- Combo to get partial product
process(A0_out, B0_out)
begin
if B0_out(0) = '0' then
P0_in <= (others => '0');
elsif B0_out(0) = '1' then
P0_in <= ("0000" & A0_out(3 downto 0));
end if;
end process;
-- Partial product Register
P0reg: process(reset, clk, P0_in)
begin
if reset = '1' then
P0_out <= (others => '0');
elsif (clk'event and clk = '1') then
P0_out <= P0_in;
end if;
end process;
-- For the next clock
-- Sign value is passed on
S1reg: process (reset, clk, S0_out)
begin
if reset = '1' then
S1_out <= '0';
elsif clk'event and clk = '1' then
S1_out <= S0_out;
end if;
end process S1reg;
-- A1 register
A1reg: Process (reset, clk, A0_out)
begin
if reset = '1' then
A1_out <= "0000";
elsif (clk'event and clk = '1') then
A1_out <= A0_out;
end if;
end process A1reg;
-- B1 register
B1reg: Process (reset, clk, B0_out)
begin
if reset = '1' then
B1_out <= "000";
elsif (clk'event and clk = '1') then
B1_out <= B0_out(3 downto 1);
end if;
end process B1reg;
-- Combo for partial product
process(B1_out, P0_out, A1_out)
begin
if B1_out(0) = '0' then
P1_in <= P0_out;
elsif B1_out(0) = '1' then
P1_in <= (P0_out(7 downto 0)) + ("000"&A1_out&'0');
end if;
end process;
-- Partial product Register
P1reg: process(reset, clk, P1_in)
begin
if reset = '1' then
P1_out <= (others => '0');
elsif clk'event and clk = '1' then
P1_out <= P1_in;
end if;
end process;
-- For the next clock
-- Sign value is passed on
S2reg: process (reset, clk, S1_out)
begin
if reset = '1' then
S2_out <= '0';
elsif clk'event and clk = '1' then
S2_out <= S1_out;
end if;
end process S2reg;
-- A2 register
A2reg: Process (reset, clk, A1_out)
begin
if reset = '1' then
A2_out <= "0000";
elsif (clk'event and clk = '1') then
A2_out <= A1_out;
end if;
end process A2reg;
-- B2 register
B2reg: Process (reset, clk, B1_out)
begin
if reset = '1' then
B2_out <= "00";
elsif (clk'event and clk = '1') then
B2_out <= B1_out(2 downto 1);
end if;
end process B2reg;
-- Combo for partial product
process(B2_out(0), P1_out, A2_out)
begin
if B2_out(0) = '0' then
P2_in <= P1_out;
elsif B2_out(0) = '1' then
P2_in <= P1_out(7 downto 0) + ("00"&A2_out&"00");
end if;
end process;
-- Partial product Register
P2reg: process(reset, clk, P2_in)
begin
if reset = '1' then
P2_out <= (others => '0');
elsif clk'event and clk = '1' then
P2_out <= P2_in;
end if;
end process;
-- For the next clock
-- Sign value is passed on
S3reg: process (reset, clk, S2_out)
begin
if reset = '1' then
S3_out <= '0';
elsif clk'event and clk = '1' then
S3_out <= S2_out;
end if;
end process S3reg;
-- A3 register
A3reg: Process (reset, clk, A2_out)
begin
if reset = '1' then
A3_out <= "0000";
elsif (clk'event and clk = '1') then
A3_out <= A2_out;
end if;
end process A3reg;
-- B3 register
B3reg: Process (reset, clk, B2_out)
begin
if reset = '1' then
B3_out <= '0';
elsif (clk'event and clk = '1') then
B3_out <= B2_out(1);
end if;
end process B3reg;
-- Combo for partial product
process(B3_out, P2_out, A3_out)
begin
if B3_out = '0' then
Pp3_out <= P2_out;
elsif B3_out = '1' then
Pp3_out <= (P2_out(7 downto 0)) + ('0'&A3_out&"000");
end if;
end process;
ComboResult: Process(Pp3_out, S3_out)
begin
if S3_out = '0' then
P3_in <= Pp3_out;
elsif S3_out = '1' then
P3_in <= not(Pp3_out) + 1;
end if;
end process;
-- Final product Register
P3reg: process(reset, clk, P3_in)
begin
if reset = '1' then
P3_out <= (others => '0');
elsif clk'event and clk = '1' then
P3_out <= P3_in;
end if;
end process;
-- Output of the final product
Pout <= P3_out;
end Behavioral;