VHDL Design for an Up-down Counter
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-- Company: Computer Science Department
-- Engineer: Guili Liu
--
-- Create Date: 10:38:58 10/31/2009
-- Design Name: counter.vhd
-- Module Name: counter - Behavioral
-- Project Name: counter
-- Target Devices: xc2vp30-6ff1152
-- Tool versions:
-- Description: This is the top level HDL file for an up/down counter
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity counter is
Port ( CLOCK : in STD_LOGIC;
DIRECTION : in STD_LOGIC;
COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0));
end counter;
architecture Behavioral of counter is
signal count_int: std_logic_vector(3 downto 0) := "0000";
begin
process (CLOCK)
begin
if CLOCK'event and CLOCK = '1' then
if DIRECTION = '1' then
count_int <= count_int + 1;
else
count_int <= count_int - 1;
end if;
end if;
end process;
COUNT_OUT <= count_int;
end Behavioral;