# Using VHDL to Describe Flip-Flops and Registers

## Objectives

```
Using different VHDL methods to describe the Flip-Flops
Investigating registers
Using VHDL to describe registers

```

## 1. D-Flip-Flop

Flip-Flops are basic storage/memory elements. A sequential circuit consists of a combinational circuit and storage elements (flip-flops) that together form a feedback system. We have learned quite a few of flip-flops in CS201. In this lab we are going to see how to use VHDL to describe flip-flops.

D-flip-flop is a very useful storage element. Its present state-next state table demonstrates the behavior of a D-flip-flop.
It has the following characteristics:

```
Characteristic equation:	Q(t+1) = D

Characteristic Table            Excitation Table
====================            ===================
D  Q(t+1)  Operation            Q(t)  Q(t+1)   D
====================            ===================
0    0     Reset                 0      0      0
--------------------            -------------------
1    1     Set                   0      1      1
====================            -------------------
1      0      0
-------------------
1      1      1
===================

```
We can use VHDL models to describe it also.

### Create D-Flip-Flop using process and if statement

For the D-flip-flop symbol and the truth table below,
```

Truth Table
==================
ena	d	q
------------------
0	0	Hold
0	1	Hold
1	0	0
1	1	1
------------------

```
we can have the following VHDL code for it:
```
library IEEE;
use IEEE.std_logic_1164.all;

entity dffv1 is

port(
d	: in	std_logic;
ena	: in	std_logic;
q	: out	std_logic
);

end dffv1;

architecture arch1 of dffv1 is
begin

process (d, ena)
begin
if (ena = '1') then
q <= d;
end if;
end process;

end arch1;

```
Here is another version of VHDL description of a D-flip-flop.
You may have noticed that this version has set and reset signals.
When S is set to 1, Q = 1 and Qbar = 0; when R is set to 1, Q = 0 and Qbar = 1.
Here is a symbol for it:
```

```
We can use VHDL to describe it as follows:
```
library IEEE;
use IEEE.std_logic_1164.all;

entity dffv2 is

port(
EN	: in	std_logic;
D	: in	std_logic;
Q	: out	std_logic;
Qbar	: out	std_logic;
S	: in	std_logic;
R	: in	std_logic
);

end dffv2;

architecture behavior of dffv2 is

begin

-- Your VHDL code defining the model goes here
process (D, EN, R, S)
begin
if (R = '1') then
Q <= '0';
Qbar <= '1';
elsif  (S = '1') then
Q <= '1';
Qbar <= '0';
elsif  (en = '1') then
q <= D;
Qbar <= (not D);
end if;
end process;

end behavior;

```

### Create D-Flip-Flop with clock

For the following symbol,
```

```
we have the corresponding VHDL description below:
```
library IEEE;
use IEEE.std_logic_1164.all;

entity dffv3 is

port(
D	: in	std_logic;
clk	: in	std_logic;
Qbar	: out	std_logic;
Q	: out	std_logic
);

end dffv3;

architecture bhav of dffv3 is

begin

-- Your VHDL code defining the model goes here
process (d, clk)
begin
-- clock rising edge
if (clk'event and clk='1') then
q <= d;
Qbar <= not d;
end if;
end process;

end bhav;

```
Can you improve this D-Flip-Flop by adding the Reset and Set inputs? Try it yourself.

### Create D-Flip-Flop using wait statement

The various WAIT statements explicitly specify the conditions under which a process may resume execution after being suspended. The forms of the WAIT statement include the following:
```
wait for time expression;   e.g. wait for 10 ns;
wait on signal;		    e.g. wait on clk;
wait until condition;	    e.g. wait until(clk'event and clk = '1');
wait;

```
For this symbol, the corresponding VHDL code follows.
```

```
```
library IEEE;
use IEEE.std_logic_1164.all;

entity dff is

port(
D	: in	std_logic;
CLK	: in	std_logic;
Q	: out	std_logic;
Qbar	: out	std_logic
);

end dff;

architecture arch1 of dff is

begin

-- Your VHDL code defining the model goes here
output: process
begin
wait until (CLK'event and CLK = '1');
Q <= D after 10 ns;
Qbar <= not D after 10 ns;
end process output;
end arch1;

```
You are going to create VHDL models for JK-flip-flops for your lab assignment.

### JK-flip-flops

Here is a quick review of the JK-flip-flop.

The JK flip-flop is very flexible and therefore allows simpler circuit designs. You are going to create VHDL models for the negative edge triggered JK flip-flops (i.e it allows the signal to change on the negative edge of the clock). The present state-next state table below demonstrates the behavior of the flip-flop.

```
The characteristic equation is Q(t+1) = JQ'(t) + K'Q(t).

Characteristic Table                    Excitation Table
==========================            ===================
J  K  Q(t+1)  Operation               Q(t)  Q(t+1)  J  K
==========================            ===================
0  0  Q(t)    No Change               0     0       0  x
--------------------------            -------------------
0  1  0       Reset                   0     1       1  x
--------------------------            -------------------
1  0  1       Set                     1     0       x  1
--------------------------            -------------------
1  1  Q'(t)   Complement              1     1       x  0
==========================            ===================

```

## 2. A Brief Introduction to Registers

Flip-flops are generally found in programmable logic device (PLD) as registered output. That means an output of a PLD having a flip-flop (usually D-flip-flop) that stores the output state. A register is one or more flip-flops used to store data. In other words, a register is a digital circuit such as a flip-flop or an array of flip-flops that stores one or more bits of digital information.

The shift register is one important kind. The following table shows you more information about shift registers.

```
Shift Register        -	A synchronous sequential circuit that will
store and move n-bit data, either serially
or in parallel, in n flip-flops.

Serial Shifting	     -  Movement of data from one end of a shift register
to the other at a rate of one bit per clock pulse.

Parallel Transfer    -  Movement of data into all flip-flops of a
shift register at the same time.

Rotation	     -  Serial shifting of data with the output(s) of
the last flip-flop connected to the synchronous
input(s) of the first flip-flop.  The result
is continuous circulation of the same data.

Right Shift	     -  A movement of data from the left to the right
in a shift register.

Left Shift	     -  A movement of data from the right to the left
in a shift register.

Bidirectional Shift Register - A shift register that can serially shift
bits left or right according to the state of a
direction control input.

Parallel Load Shift Register - A shift register that can be preset to
into it's internal flip-flops.

Universal Shift Register     - A shift register that can operate with
combination of serial and parallel inputs and outputs.
That is, serial in/serial out,
serial in/parallel out,
parallel in/serial out,
parallel in/parallel out.
A universal shift register is often bidirectional,
as well.

```
The following picture shows the data movement in a 4-bit shift register.
```

```
The next picture shows a circuit of a 4-bit serial shift register designed to shift right. To make other shift registers, extra gates are needed.
```

```

## 3. Using VHDL to Describe Registers

The shift registers can be programmed in VHDL by taking different approaches.
• Structural design
- a VHDL design technique that connects pre-designed components using internal signals.
• Dataflow design
- a VHDL design technique that uses Boolean equations to define relationships between inputs and outputs.
• Behavioral design
- a VHDL design technique that uses descriptions of required behavior to create the design.
In the following sections, we will look at 4-bit shift registers.

### Structural Design

Structural design is like taking components out of a bin and connecting them together to make a circuit. We can use a D-Flip-Flop that was already created, and instantiate it four times to make a 4-bit shift register with connections made by internal signals. We have used this technique for building the 4-bit parallel adder in lab 5. You may try this approach to build a 4-bit shift register by yourself.

### Dataflow Design

```
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity sreg4dflw is

port(
serial_in	: in	std_logic;
clk	: in	std_logic;
q	: out	std_logic_vector(3 downto 0));

end sreg4dflw;

architecture right_shift of sreg4dflw is

signal d: std_logic_vector(3 downto 0);
begin

-- Your VHDL code defining the model goes here
process (clk)
begin
-- Define a 4-bit d-flip-flop
if (clk'event and clk = '1') then
q <= d;
end if;
end process;

d <= serial_in & q(3 downto 1);
-- This is equivalent to the following code:
-- d(3) <= serial_in;
-- d(2) <= q(3);
-- d(1) <= q(2);
-- d(0) <= q(1);

end right_shift;

```

### Behavior Design

```
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity sreg4behv is

port(
serial_in	: in	std_logic;
clk	: in	std_logic;
q	: out	std_logic_vector(3 downto 0)
);

end sreg4behv;

architecture right_shift of sreg4behv is

begin

-- Your VHDL code defining the model goes here
process (clk)
begin
-- Define a 4-bit d-filp-flop
if (clk'event and clk = '1') then
q <= serial_in & q(3 downto 1);
end if;
end process;

end right_shift;

```