When designing combinational circuits. We discussed six steps:
We will look at designing a combinational circuit for a Half-Adder.
1 + 1 = 10 where sum = 0, carry = 1 0 + 1 = 01 where sum = 1, carry = 0
Fill in the empty boxes with what you think c and s should be:
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c |
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Here is where we cheat a little. We will not use the Karnaugh maps. Because you have a simple truth table (4 rows), you can match the gates with the gates you already know.
Here are the truth tables for the gates you know:
A B | AND | NAND | NOR | OR | XOR |
0 0 | 0 | 1 | 1 | 0 | 0 |
0 1 | 0 | 1 | 0 | 1 | 1 |
1 0 | 0 | 1 | 0 | 1 | 1 |
1 1 | 1 | 0 | 0 | 1 | 0 |
We could from here draw a circuit with two inputs, two gates, and two outputs, but you want to learn something new, right? This is where we will lead into the next section on devices.
The purpose of learning how to make a device is so that we can turn our half-adder into a "black box" where the gates inside are hidden and all we see is the input and the output. We can then combine these half-adder devices to make things like full-adders and half-subtractors.
Please follow these steps to create your own half-adder device:
Now, we need to create a device out of this circuit.
Once you have the device created, you will have to save it to a library so that you can create circuits that contain this device.
Note: You can use the same library to store the different devices that you will create in the lab exercise (in other words, steps 1 and 2 below only need to be done once for this lab)
If something is not working how you expect it, you can always double click on the Half Adder Device on the workspace and it will take you to the underlying circuit.
You can now try and use two half-adders to create a full adder. Again, we will break the problem into steps:
1 + 1 + 1 = 11 where sum = 1, carry = 1 1 + 0 + 1 = 10 where sum = 0, carry = 1
Fill in the truth table with what you think ci+1 and s should be. A few have already been filled in for you.
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ci+1 |
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1 |
Here, you could use a Karnaugh Map to reduce the problem and draw the circuit. We want to use two half-adders and some additional gate.
Again, just looking at the truth table, we can see that one of the outputs (ci+1 or s) uses XOR gates. How do I know that? XOR enables you to do a parity check. The idea is: when there is an odd number of 1 bits, the XOR results are 1, otherwise they are 0. For instance
1 XOR 1 XOR 0 = 0 (Notice that there are two 1-bits)
1 XOR 0 XOR 0 = 1 (Notice that there is one 1-bit)
We can hook up inputs into two half adders devices to get the results of the two XORS. How do we do that?
What's left? Figure out what's coming out of the outputs that aren't from the XOR gate.
What additional gate do we need? You may have to use the Karnaugh map.
When you try this project on another machine, you might not find your library in the library list. To access your library, right click on the "parts preview pane" to get the menu shown below:
Select "Open Lib..." and navigate to your library.