CS201 Design Adders Lab

CS201 Lab: Design Adders & Subtractors

Objectives

Review

When designing combinational circuits. We discussed five steps:

  1. Define/Describe/State the problem
  2. Determine the number of variables needed and assign letter symbols to the input and output variables
  3. Construct the function table that defines the relationship between the inputs and outputs
  4. Simplify the boolean expression for each output. This is done with Karnaugh Maps or Boolean algebra
  5. Draw the logic diagram and implement the circuit in Logisim

We will look at designing a combinational circuit for a Half-Adder.

Half-Adder

1. State the Problem:

2. Assign Variables:

3. Construct the Function Table:

You should be able to fill in the boxes for c and s:

Input
 
Output
x
y
 
c
s
0
0
 
0
1
 
1
0
 
1
1
 

4. Simplify

Here is where we cheat a little. We will not use the Karnaugh maps. Because you have a simple truth table (4 rows), you can match the gates with the gates you already know.

Here are the truth tables for the gates you know:

x     y AND NAND NOR OR XOR
0     0 0 1 1 0 0
0     1 0 1 0 1 1
1     0 0 1 0 1 1
1     1 1 0 0 1 0

We can get the following expressions by observation. There are two inputs, two gates, and two outputs.

        s = x XOR y 
        c = xy 

5. Draw the Logic Diagram and implement it in Logisim

You can draw circuits from the above expressions.


 

Full-Adder

You can now try and use two half-adders to create a full adder. Again, we will break the problem into steps:

1. State the Problem:

2. Assign Variables:

3. Construct the Function Table:

Fill in the truth table with what you think ci+1 and s should be. A few have already been filled in for you.

Input
 
Output
x
y
ci
 
ci+1
s
0
0
0
 
0
0
1
 
0
1
0
 
0
1
1
 
1
0
0
 
1
0
1
 
1
0
1
1
0
 
1
1
1
 
1
1

4. Simplify

You can use the Karnaugh Map reduction method to find the simplfied expressions and then draw the full adder circuit.

Here are the functions for your convenience.

	s = x XOR y XOR ci
	ci+1 = xy + ci(x XOR y)

5. Draw Logic Circuit

You can draw circuits from these expressions and find that a full adder can be designed by using two "Half Adders" and one additional OR gate.


 


Assignments



Copyright: Department of Computer Science, University of Regina.