CS201 Lab: Build a 4-bit Shift register Device
Design Sequential Adder and Subtractor

Objectives

Build a 4-bit shift register and use it to store 4-bit values  
Review the definition of half-adder and full adder
Examine an binary adder-subtractor 
Build sequential adder, subtractor, and adder-subtractor circuits to verify the suquential design procedures

Design a 4-bit Shift Register:

Build a 4-bit right shift register device using four D-flip-flops
and some one-bit tri-state buffers.

We can use a LD control over it.

When LD = 0, your register will be able to do parallel loading.

When LD = 1, it will be able to shift right one bit (i.e.  SI -> Q3 -> Q2 -> Q1 -> Q0).

Here is some info about the one-bit tri-state buffer for your reference:

1).A  one-bit tri-state buffer can be obtained from the "Simulation Logic.clf" libruary.

2).A testing circuit and its truth table are as follows:

  
A 4-bit Shift Register Circuit



        



        It demonstrates the following:

                1.      How to use the 4 bit shift register.

                2.      How to use the Load and Shift modes.

                3.      How to use individual probes on each output to make
                        it easier to see what's happening in shift mode.

                4.      Shifting direction is SI -> Q3 -> Q2 -> Q1 -> Q0.

	With LD set to 1:

                The register is in shift right mode;
                The SI (shift input) line is used to set the value to be
                shifted into the register. Clocking is positive edge triggered.


        With LD set to 0:

                The register is in parallel load mode.
                Inputs D0 to D3 become outputs Q0 to Q3 on the next
                rising clock pulse.

        

        You are asked to create a 4-bit Shift Register device in the lab assignment.
        

        Here is the image of the testing circuit.
        

        
        



        It can be used to store and diplay the output of your  sequential adder, subtractor, and adder-subtractor
        circuits in the lab assignment.

  

Half-Adder

    A Half-adder is a combinational circuit that performs the addition of 2 bits.

	Inputs: 	2 input bits to be added 

	Outputs: 	sum bit (least significant) 
			carry bit (most significant)  

    For example: 

	1 + 1 = 1 0 		c = 1;  s = 0

	1 + 0 = 0 1		c = 0;  s = 1
      

Full-Adder

    A Full-adder is a combinational circuit that forms the arithmetic sum of 3 input bits.

	Inputs: 	2 input bits to be added (x, y) 
			1 carry bit from previous lower significant position (z)  

	Outputs: 	sum bit (least significant) 
			carry bit (most significant) 

    For example: 

	1 + 1 + 1 = 1 1 	c = 1;  s = 1
	1 + 0 + 1 = 1 0		c = 1;  s = 0
	      

    Note: it takes 2 half-adders to make a full adder.

Binary Adder-Subtractor

A binary adder is the circuit that generates the arithmetic sum of 
two binary numbers of any length. 

The subtraction of binary numbers can be done most conveniently 
by means of complements of numbers. 

Subtraction A - B can be done by taking the 2's complement of B and 
adding it to A. 

The 2's complement can be obtained by taking the 1's complement and 
adding 1 to the least significant pair of bits. 

The 1's complement can be implemented with inverters and 
a 1 can be added to the sum through the input carry. 

The addition and subtraction operations can be combined into one common 
circuit by including an exclusive-OR (XOR) gate with a full-adder. 

A bit sequential adder-subtractor is shown in the following figure:
	

	
	

Input X is used to represent the bit of the binary number A. 
Input Y is used to represent the bit of the binary number B. 
The control signal Z controls the type of operation. 

When Z = 0 the circuit is an adder, meanwhile, the D flip-flop 
should be initialized to 0. 
When Z = 1 the circuit becomes a subtractor. The D flip-flop
should be initialized to 1. 

The XOR gate receives input of signal bit Z and the input of the operand bit Y.

When Z = 0, we have Y XOR Z = Y. 
--------------------------------
The full adder receives the value of Y, the input carry is 0 because 
D flip-flop was initialized to 0, and the circuit performs A plus B. 

When Z = 1, we have Y XOR Z = Y' and the initial carry to 1. 
------------------------------------------------------------
The Y input is complemented and a 1 is added through the initial input carry. 
The circuit performs the operation: A plus the 2's complement of B. 

For unsigned numbers A and B, this gives the A - B if A >= B or 
2's complement of (B - A) if A < B. 

For signed numbers, the result is A - B provided there is no overflow. 

Assignments