Using VHDL to Describe Counters

Objectives of this lab:

	To learn more about VHDL Syntax structures.
	To create VHDL Models for counters with LogicWorks 5.

Preparation

	Read lab lecture notes. 

Lab Assignments

1. Build a 4-bit UP-DOWN counter device with a VHDL Model.

• The counter will be able to load a new number if the "Load" signal is '1'.
• The counter will be able to count if the "Load" signal is '0'.
• The counter counts when the clock goes up.
• The counter counts up when the direction signal "DR" is set to '1'.
• The counter counts down when the direction signal "DR" is set to '0'.
• Create a VHDL Model for a Device Symbol "COUNT4updw".
• Build a simple circuit by connecting some I/O devices such as hex keyboard, hex display, and binary switches to test your new counter.

  Hand in the following:

• Print out of your VHDL Model file for the 4-bit UP-DOWN counter.
• Print out of the circuit with the newly created device of your 4-bit UP-DOWN Counter to test it.
• Show your lab instructor that your circuit works during your lab time.
  Please include the following text by your circuit
  • When LD=1
  • clock toggle does not cause change in output
  • change in hex keyboard causes change in output
  • change in LD from 0 to 1, causes current hex keyboard settings to be output
  • change in DR does not affect output
  • Counter counts down to 0 and wraps to F when DR= '0'
    
    • responds on positive edge
  • Counter counts up to F and wraps to 0 when DR= '1'
    
    • responds on positive edge

2. Build a counter device with a VHDL Model to simulate a regular clock face.

• The counter will be able to load a new number if the load signal is '1'.
  • The number displayed should be from 1 to C (12).
  • If D to F and 0 are loaded, they should be mapped to C.
• The counter counts up by one when the system clock goes up.
• Create a VHDL Model for a Device Symbol "mod12counter".
• Build a simple circuit by connecting some I/O devices such as hex keyboard, hex display, and binary switches to test your Modulo-12 counter.

  Hand in the following:

• Print out of your VHDL Model file for the Modulo-12 counter.
• Print out of the circuit with the newly created device of your Modulo-12 Counter to test it.
• Show your lab instructor that your circuit works during your lab time.
  Please include the following text by your circuit
  • When LD=1
  • clock toggle does not cause change in output
  • change in hex keyboard causes change in output
  • change in LD from 0 to 1, causes current hex keyboard settings to be output
  • D, E, F, 0 on hex keyboard will be output as C
  • Counter counts up to C
  • after C, counter wraps to 1
  • responds on positive edge
  • After loading D, E, F, or 0, counter will count up from 1
    • responds on positive edge

3. Build a 3-bit counter device with a VHDL Model.

• The counter follows the given sequence: 0 -> 2 -> 3 -> 4 -> 7 -> 0.
• Route the unused states to state 7 if you need.
• When the input Load is set to 1, the input Din is loaded to the current state.
• When the input Load is set to 0, the counter moves to the next state when clock goes up.
• You will dislay the current state as an output of your device.
• Create a VHDL Model for a Device Symbol "Counter201".
• Build a simple circuit by connecting some I/O devices such as binary switches and bineray probes to test your Counter201.

  Hand in the following:

• Print out of your VHDL Model file for the Counter201.
• Print out of the circuit with the newly created device of your Counter201 to test it.
• Show your lab instructor that your circuit works during your lab time.
  Please include the following text on your circuit
  • When Load = 1
  • clock toggle does not cause change in output
  • change in input switches causes change in output
  • When Load = 0
  • The counter proceeds as the given sequence: 0 -> 2 -> 3 -> 4 -> 7 -> 0
  • responds on positive edge
  • change in Load from 0 to 1, causes current Din input be output

Questions

	1.	What is the Modulus of a counter?
	2.	What does a Modulo-12 counter mean?

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Copyright: Department of Computer Science, University of Regina.