Count Sequence - The specific series of output states through which a counter progresses. Modulus - The number of states through which a counter sequences before repeating. Recycle - It makes a transition from the last state of the count sequence to the first state. Up Counter - A counter with an ascending sequence. Down Counter - A counter with a descending sequence. Modulo-n (or mod-n) Counter is a counter with a modulus n. Modulo Arithmetic is a closed system of counting and adding, whereby a sum greater than the largest number in a sequence "rolls over" and starts from the beginning of the sequence. For Example, a regular clock is a typical counter. On its face, there are 12 states. It is a Modulo-12 counter. We know 4 hours after 10:00 a.m. is 2:00 p.m. In the mod-12 system, 10+4 = 2.In CS201, you have learned how to use sequential design procedure to build a counter. In the next section, you will see an example of using VHDL to describe a counter.
This counter can be described in VHDL as follows:
library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity COUNT8 is port( DIN : in std_logic_vector(7 downto 0); CLK : in std_logic; LOAD : in std_logic; DOUT : out std_logic_vector(7 downto 0) ); end COUNT8; architecture behavior of COUNT8 is begin -- notice the process statement and the variable COUNT clk_proc:process(CLK) variable COUNT:unsigned(7 downto 0) := "00000000"; begin if (CLK'EVENT AND CLK = '1') then if LOAD = '1' then COUNT := DIN; else COUNT := COUNT + 1; end if; end if; DOUT <= COUNT after 50 ns; end process clk_proc; end behavior;When using VHDL to create a counter, we can take different approaches. We can encode the Boolean equations of the counter directly with concurrent signal assignment statements; we can use VHDL code to describe the behavior of the counter; we can use CASE statement to implement the state diagram of the counter; or we may be able to use a predefined counter in the software package available to you. Using concurrent signal assignment statement is an insufficient way to code many digital functions. Therefore, it is not preferable.
The above example is using behavior description. You will use the similar method to do your lab assignment number one.
Here are some useful terms for your reference:
[label:] PROCESS (sensitivity list) BEGIN statement; END PROCESS;VHDL syntax requires an IF statement or a CASE statement to be obtained within a PROCESS.
An IF statement executes one or more VHDL statements, depending on the state of a Boolean test condition. It has the following syntax format:
IF ___expression THEN __statement; __Statement; ELSIF __expression THEN __statement; __statement; ELSE __statement; __statement; END IF;Here is the general format for the CASE statement:
__process_label: PROCESS (sensitivity list) BEGIN CASE __expression IS WHEN __constant_value => __statement; __statement; WHEN __constant_value => __statement; __statement; WHEN OTHERS => __statement; __statement; END CASE; END PROCESS __process_label;The expression in the CASE statement is usually a port or signal whose value we wish test. For that case, one or more statements can be executed.
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