Using VHDL to Describe Flip-Flops and Registers

Objectives of this lab:

	To learn more about VHDL Syntax structures.
	To create VHDL Models for flip-flops and registers with LogicWorks 5.

Preparation

	Read lab lecture notes. 

Lab Assignments

1. Build a JK-Flip-Flop device with a VHDL Model.

	
	For the following symbol and truth table, develop VHDL
	code for it.

	


	Truth Table
	=============================================
	J	K	clk		Q	Qbar
	---------------------------------------------
	0	0	falling edge	hold	hold
	0	1	falling edge	0	1
	1	0	falling edge	1	0
	1	1	falling edge	toggle	toggle
	----------------------------------------------

Hand in the following:

• Print out of your VHDL Model file for the JK-flip-flop.
• Print out of the circuit with the newly created device of
  your JK-flip-flop to test its expected behavior in the truth table.
• Show your lab instructor that your JK-flip-flop behaves as expected during the lab time.
  Please include the JK truth table from above for marking purposes.

2. Build a 4-bit shift register device with a VHDL Model.

	

	Description of the requirement:

	1.	All activities happen when the clock goes up.
	2.	When LD = 1, load value from D to the register showing at Q.
	3.	When LD = 0, the register will shift one bit to right.
		i.e.   Q1 -> Q0, Q2 -> Q1, Q3 -> Q2, SI -> Q3.

• Create a VHDL Model for a Device Symbol "Sreg4rload".
• Build a simple circuit by connecting some I/O devices such as hex keyboard, hex display, binary switches, and binary probes to verify the output of your 4-bit right shift register device.

  Hand in the following:

• Print out of your VHDL Model file for the 4-bit right shift register device.
• Print out of the circuit with the newly created 4-bit right shift register
  device to demonstrate its expected outcome with two different modes.
• Please include the following text on your circuit and test them out.
  • Testing LD = 1, D = 6:
    clock works on positive edge _________
    6 is loaded into Q line _________
  • Testing LD = 0, SI = 1:
    clock works on positive edge _________
    right shift works _________
  • Testing LD = 0, SI = 0:
    clock works on positive edge _________
    right shift works _________
  • Random LD works _________
  • Random Shift works _________

Questions

	1.	What is a register?  What is a right shift register?
	2.	What kind of approaches could be used to describe a register
		in VHDL?

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Copyright: Department of Computer Science, University of Regina.