Using VHDL to Describe Flip-Flops and Registers

Objectives of this lab:


	To learn more about VHDL Syntax structures.
	To create VHDL Models for flip-flops and registers with LogicWorks 5.

Preparation


	Read lab lecture notes. 

Lab Assignments

1. Build a JK-Flip-Flop device with a VHDL Model.

2. Build a 4-bit shift register device with a VHDL Model.


Questions


	1.	What is a register?  What is a right shift register?
	2.	What kind of approaches could be used to describe a register
		in VHDL?


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Monday, 22-Oct-2012 11:56:10 CST
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Copyright: Department of Computer Science, University of Regina.